MT9VDDT6472PHG-335F2 Micron Technology Inc, MT9VDDT6472PHG-335F2 Datasheet - Page 24
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MT9VDDT6472PHG-335F2
Manufacturer Part Number
MT9VDDT6472PHG-335F2
Description
MODULE DDR SDRAM 512MB 200SODIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT9VDDT1672PHG-335D2.pdf
(33 pages)
Specifications of MT9VDDT6472PHG-335F2
Memory Type
DDR SDRAM
Memory Size
512MB
Speed
333MT/s
Package / Case
200-SODIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
200SODIMM
Device Core Size
72b
Organization
64Mx72
Total Density
512MByte
Chip Density
512Mb
Access Time (max)
700ps
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
1.4A
Number Of Elements
9
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
200
Mounting
Socket
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT9VDDT6472PHG-335F2
Manufacturer:
MICRON
Quantity:
1 001
Table 18: PLL Clock Driver Timing Requirements and Switching Characteristics
Note: 1
NOTE:
pdf: 09005aef808ffe58, source: 09005aef808ffdc7
DD9C16_32_64_128x72PHG.fm - Rev. B 9/04 EN
PARAMETER
Operating Clock Frequency
Input Duty Cycle
Stabilization Time
Cycle to Cycle Jitter
Static Phase Offset
Output Clock Skew
Period Jitter
Half-Period Jitter
Input Clock Slew Rate
Output Clock Slew Rate
1. The timing and switching specifications for the PLL listed above are critical for proper operation of DDR SDRAM
2. The PLL must be able to handle spread spectrum induced skew.
3. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required
4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its
5. Static Phase Offset does not include Jitter.
6. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each
7. The Output Slew Rate is determined from the IBIS model:
modules. These are meant to be a subset of the parameters for the specific device used on the module. Detailed
information for this PLL is available in JEDEC Standard JESD82.
to meet the other timing parameters. (Used for low-speed system debug.)
reference signal after power up.
other.
SYMBOL
t
t
t
JIT
t
STAB
JIT
t
t
t
JIT
f
t
SK
t
LS
DC
CK
LS
HPER
PER
CC
O
O
I
128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)
MIN
-100
-75
-50
-75
1.0
1.0
60
40
-
-
V
24
0°C
DD
NOMINAL
CDCV857
= +2.5V ±0.2V
GND
V
DD
T
0
-
-
-
-
-
-
-
-
-
A
200-PIN DDR SDRAM SODIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
+70°C
V
V
CK
CK
R=60
R=60
MAX
170
100
100
100
60
75
50
75
4
2
V
DD
/2
©2004 Micron Technology, Inc. All rights reserved.
UNITS
MHz
V/ns
V/ns
ms
%
ps
ps
ps
ps
ps
ADVANCE
NOTES
2, 3
4
5
6
6
7