MT9VDDT6472PHG-335F2 Micron Technology Inc, MT9VDDT6472PHG-335F2 Datasheet - Page 29

• Manufacturer Part Number: MT9VDDT6472PHG-335F2
• Description: MODULE DDR SDRAM 512MB 200SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT9VDDT6472PHG-335F2

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 333MT/s
• Package / Case: 200-SODIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 200SODIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 512Mb
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 1.4A
• Number Of Elements: 9
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 200
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 23: Serial Presence-Detect Matrix – 128MB, 256MB, 512MB
“1”/”0”: Serial Data, “driven to HIGH”/”driven to LOW”
pdf: 09005aef808ffe58, source: 09005aef808ffdc7
DD9C16_32_64_128x72PHG.fm - Rev. B 9/04 EN
BYTE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
1
2
3
4
5
6
7
8
9
Number of SPD Bytes Used by Micron
Total Number of Bytes in SPD Device
Fundamental Memory Type
Number of Row Addresses on Ass’y
Number of Column Addresses on Ass’y
Number of Physical Ranks on DIMM
Module Data Width
Module Data Width (Continued)
Module Voltage Interface Levels
SDRAM Cycle Time,
2.5) (see note 2)
SDRAM Access from Clock,
Latency = 2.5) (see note 1)
Module Configuration Type
Refresh Rate/ Type
SDRAM Device Width (Primary DDR
SDRAM)
Error-checking DDR SDRAM Data
Width
Minimum Clock Delay, Back-to-Back
Random Column Access
Burst Lengths Supported
Number of Banks on DDR SDRAM Device
CAS Latencies Supported
CS Latency
WE Latency
SDRAM Module Attributes
SDRAM Device Attributes: General
SDRAM Cycle Time,
note 2)
SDRAM Access from CK,
(See note 2)
SDRAM Cycle Time,
SDRAM Access from CK,
Minimum Row Precharge Time,
(see note 5)
Minimum Row Active to Row Active,
t
Minimum RAS# to CAS# Delay,
(see note 5)
Minimum RAS# Pulse Width,
note 3)
Module Rank Density
RRD
DESCRIPTION
t
t
t
CK (CAS Latency =
CK (CL = 2) (See
CK (CL = 1.5)
t
t
AC (CL = 2)
AC (CL = 1.5)
t
AC (CAS
t
RAS (see
t
RCD
t
128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)
RP
128MB, 256MB, 512MB
0.75ns (-262/-26A/-265)
7.5ns (-335/-262/-26A)
Unbuff, Diff CLK, PLL
15ns (-262/-26A/-265)
45ns (-262/-26A/-265)
15.6µs or 7.8µs/SELF
Fast/concurrent AP
ENTRY(VERSION)
0.75ns (-265/-26A)
20ns (-26A/-265)
20ns (-26A/-265)
7ns (-262/-26A)
DDR SDRAM
7.5ns (-265)
0.7ns (-335)
0.7ns (-335)
10ns (-265)
18ns (-335)
15ns (-262)
12ns (-335)
18ns (-335)
15ns (-262)
42ns (-335)
6ns (-335)
SSTL 2.5V
10 or 11
12 or13
1 clock
2, 4, 8
2, 2.5
128
256
ECC
N/A
N/A
72
1
0
8
8
4
0
1
29
200-PIN DDR SDRAM SODIMM
MT9VDDT1672PH MT9VDDT3272PH MT9VDDT6472PH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0A
A0
2A
2D
80
08
07
0C
01
48
00
04
60
70
75
70
75
02
80
08
08
01
0E
04
0C
01
02
24
00
75
70
75
00
00
48
3C
50
30
3C
48
3C
50
20
0D
0A
A0
2A
2D
0C
C0
3C
3C
3C
80
08
07
01
48
00
04
60
70
75
70
75
02
82
08
08
01
0E
04
01
02
24
75
70
75
00
00
48
50
30
48
50
40
©2004 Micron Technology, Inc. All rights reserved.
ADVANCE
0D
A0
2A
2D
80
08
07
0B
01
48
00
04
60
70
75
70
75
02
82
08
08
01
0E
04
0C
01
02
24
C0
75
70
75
00
00
48
3C
50
30
3C
48
3C
50
80