MCP3424EV Microchip Technology, MCP3424EV Datasheet - Page 17

• Manufacturer Part Number: MCP3424EV
• Description: EVALUATION BOARD FOR MCP3424
• Manufacturer: Microchip Technology

Specifications of MCP3424EV

• Number Of Adc's: 1
• Number Of Bits: 18
• Sampling Rate (per Second): 3.75 ~ 240
• Data Interface: I²C
• Inputs Per Adc: 4 Differential
• Input Range: ±2.048 V
• Power (typ) @ Conditions: 135µA @ 240sps
• Voltage Supply Source: Single Supply
• Operating Temperature: -55°C ~ 125°C
• Utilized Ic / Part: MCP3424
• Processor To Be Evaluated: MCP3424
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

FIGURE 5-1:
5.3.2
The MCP3424 has two external device address pins
(Adr1, Adr0). These pins can be set to a logic high (or
tied to V
connected to anything, or tied to V
nations of logic level using the two pins allow eight
possible addresses.
address depending on the logic status of the address
selection pins.
The device samples the logic status of the Adr0 and
Adr1 pins in the following events:
(a)
(b)
(c)
The device samples the logic status (address pins)
during the above events, and latches the values until a
new latch event occurs. During normal operation (after
the address pins are latched), the address pins are
internally disabled from the rests of the internal circuit.
© 2008 Microchip Technology Inc.
Note 1:
(See Section 5.4 “General Call”).
(See Section 5.4 “General Call”).
Device power-up.
General Call Reset
General Call Latch
Start bit
DD
1
), low (or tied to V
DEVICE ADDRESS BITS (A2, A1, A2)
AND ADDRESS SELECTION PINS.
Device Code
See
1
Table 5-3
0
Address
Address Byte
Address
MCP3424 Address Byte.
Table 5-3
1
for address bit selection
A2
Address Bits
SS
Read/Write bit
), or left floating (not
A1
DD
shows the device
Acknowledge bit
/2), These combi-
A0
(Note 1)
R/W ACK
It is recommended to issue a General Call Reset or
General Call Latch command once after the device
has powered up. This will ensure that the device reads
the address pins in a stable condition, and avoid latch-
ing the address bits while the power supply is ramping
up. This might cause inaccurate address pin detection.
When the address pin is left “floating”:
When the address pin is left “floating”, the address pin
momentarily outputs a short pulse with an amplitude of
about V
latches this pin voltage at the same time.
If the “floating” pin is connected to a large parasitic
capacitance (>20 pF) or to a long PCB trace, this short
floating voltage output can be altered. As a result, the
device may not latch the pin correctly.
It is strongly recommended to keep the “floating” pin
pad as short as possible in the customer application
PCB and minimize the parasitic capacitance to the pin
as small as possible (< 20 pF).
Figure 5-2
put at the address pin when the address pin is left
“floating”. The waveform at the Adr0 pin is captured by
using an oscilloscope probe with 15 pF of capacitance.
The device latches the floating condition immediately
after the General Call Latch command.
FIGURE 5-2:
Command and Voltage Output at Address Pin
Left “Floating”.
Float waveform (output)
at address pin
SDA
SCL
DD
/2 during the latch event. The device also
shows an example of the Latch voltage out-
General Call Latch
MCP3424
DS22088A-page 17