DM300023 Microchip Technology, DM300023 Datasheet - Page 202
DM300023
Manufacturer Part Number
DM300023
Description
KIT DEMO DSPICDEM SMPS BUCK
Manufacturer
Microchip Technology
Series
dsPIC™r
Datasheets
1.AC164335.pdf
(286 pages)
2.DM300023.pdf
(22 pages)
3.DM300023.pdf
(18 pages)
4.DM300023.pdf
(50 pages)
5.DM300023.pdf
(16 pages)
Specifications of DM300023
Main Purpose
DC/DC, Step Down
Outputs And Type
2, Non-Isolated
Voltage - Input
7 ~ 15V
Regulator Topology
Buck
Board Type
Fully Populated
Utilized Ic / Part
dsPIC30F2020
Processor To Be Evaluated
dsPIC30F202x/1010
Interface Type
RS-232
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Output
-
Voltage - Output
-
Power - Output
-
Frequency - Switching
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DM300023
Manufacturer:
Microchip Technology
Quantity:
135
Company:
Part Number:
DM300023
Manufacturer:
MICROCHIP
Quantity:
12 000
- AC164335 PDF datasheet
- DM300023 PDF datasheet #2
- DM300023 PDF datasheet #3
- DM300023 PDF datasheet #4
- DM300023 PDF datasheet #5
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- Download datasheet (5Mb)
dsPIC30F1010/202X
REGISTER 18-1:
DS70178C-page 200
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
LOCK: PLL Lock Status bit (read-only)
1 = Indicates that PLL is in lock
0 = Indicates that PLL is out of lock (or disabled)
This bit is Reset upon:
Reset on POR
Reset when a valid clock switching sequence is initiated by the clock switch state machine
Set when PLL lock is achieved after a PLL start
Reset when lock is lost
Read zero when PLL is not selected as a Group 1 system clock
PRCDEN: Pseudo Random Clock Dither Enable bit
1 = Pseudo random clock dither is enabled
0 = Pseudo random clock dither is disabled
CF: Clock Fail Detect bit (read/clearable by application)
1 = FSCM has detected clock failure
0 = FSCM has NOT detected clock failure
This bit is Reset upon:
Reset on POR
Reset when a valid clock switching sequence is initiated by the clock switch state machine
Set when clock fail detected
TSEQEN: FRC Tune Sequencer Enable bit
1 = The TUN<3:0>, TSEQ1<3:0>,
0 = The TUN<3:0> bits in OSCTUN register tunes the FRC oscillator
Unimplemented: Read as ‘0’
OSWEN: Oscillator Switch Enable bit
1 = Request oscillator switch to selection specified by NOSC<1:0> bits
0 = Oscillator switch is complete
This bit is Reset upon:
Reset on POR
Reset after a successful clock switch
Reset after a redundant clock switch
Reset after FSCM switches the oscillator to (Group 3) FRC
ters sequentially tune the FRC oscillator. Each field being sequentially selected via the
ROLL<2:0> signals from the PWM module.
OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
Preliminary
...
, TSEQ7<3:0> bits in the OSCTUN and the OSCTUN2 regis-
© 2006 Microchip Technology Inc.
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