DM300023 Microchip Technology, DM300023 Datasheet - Page 54

• Manufacturer Part Number: DM300023
• Description: KIT DEMO DSPICDEM SMPS BUCK
• Manufacturer: Microchip Technology
• Series: dsPIC™r

Specifications of DM300023

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 2, Non-Isolated
• Voltage - Input: 7 ~ 15V
• Regulator Topology: Buck
• Board Type: Fully Populated
• Utilized Ic / Part: dsPIC30F2020
• Processor To Be Evaluated: dsPIC30F202x/1010
• Interface Type: RS-232
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Voltage - Output: -
• Power - Output: -
• Frequency - Switching: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC30F1010/202X
REGISTER 5-1:
DS70178C-page 52
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
SFTACERR
NSTDIS
R/W-0
R/W-0
NSTDIS: Interrupt Nesting Disable bit
1 = Interrupt nesting is disabled
0 = Interrupt nesting is enabled
OVAERR: Accumulator A Overflow Trap Flag bit
1 = Trap was caused by overflow of Accumulator A
0 = Trap was not caused by overflow of Accumulator A
OVBERR: Accumulator B Overflow Trap Flag bit
1 = Trap was caused by overflow of Accumulator B
0 = Trap was not caused by overflow of Accumulator B
COVAERR: Accumulator A Catastrophic Overflow Trap Enable bit
1 = Trap was caused by catastrophic overflow of Accumulator A
0 = Trap was not caused by catastrophic overflow of Accumulator A
COVBERR: Accumulator B Catastrophic Overflow Trap Enable bit
1 = Trap was caused by catastrophic overflow of Accumulator B
0 = Trap was not caused by catastrophic overflow of Accumulator B
OVATE: Accumulator A Overflow Trap Enable bit
1 = Trap overflow of Accumulator A
0 = Trap disabled
OVBTE: Accumulator B Overflow Trap Enable bit
1 = Trap overflow of Accumulator B
0 = Trap disabled
COVTE: Catastrophic Overflow Trap Enable bit
1 = Trap on catastrophic overflow of Accumulator A or B enabled
0 = Trap disabled
SFTACERR: Shift Accumulator Error Status bit
1 = Math error trap was caused by an invalid accumulator shift
0 = Math error trap was not caused by an invalid accumulator shift
DIV0ERR: Arithmetic Error Status bit
1 = Math error trap was caused by a divided by zero
0 = Math error trap was not caused by an invalid accumulator shift
Unimplemented: Read as ‘0’
MATHERR: Arithmetic Error Status bit
1 = Overflow trap has occurred
0 = Overflow trap has not occurred
ADDRERR: Address Error Trap Status bit
1 = Address error trap has occurred
0 = Address error trap has not occurred
DIV0ERR
OVAERR
R/W-0
R/W-0
INTCON1: INTERRUPT CONTROL REGISTER 1
W = Writable bit
‘1’ = Bit is set
OVBERR
R/W-0
U-0
—
COVAERR
MATHERR
R/W-0
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
COVBERR
ADDRERR
R/W-0
R/W-0
STKERR
OVATE
R/W-0
R/W-0
© 2006 Microchip Technology Inc.
x = Bit is unknown
OSCFAIL
OVBTE
R/W-0
R/W-0
COVTE
R/W-0
U-0
—
bit 8
bit 0