EVAL-ADUC812QS Analog Devices Inc, EVAL-ADUC812QS Datasheet - Page 14

• Manufacturer Part Number: EVAL-ADUC812QS
• Description: KIT DEV FOR ADUC812 QUICK START
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC812QS

• Rohs Status: RoHS non-compliant
• Contents: Evaluation Board, Power Supply, Cable, Software and Documentation
• For Use With/related Products: ADuC812

ADuC812
ADCCON2—(ADC Control SFR #2)
The ADCCON2 register controls ADC channel selection and conversion modes as detailed below.
SFR Address
SFR Power-On Default Value
L
ADCCON2.7 ADCI
ADCCON2.6 DMA
ADCCON2.5 CCONV
ADCCON2.4 SCONV
ADCCON2.3 CS3
ADCCON2.2 CS2
ADCCON2.1 CS1
ADCCON2.0 CS0
ADCCON3—(ADC Control SFR #3)
The ADCCON3 register gives user software an indication of ADC busy status.
SFR Address
SFR Power-On Default Value
Bit Location Bit Status
ADCCON3.7 BUSY
ADCCON3.6 RSVD
ADCCON3.5 RSVD
ADCCON3.4 RSVD
ADCCON3.3 RSVD
ADCCON3.2 RSVD
ADCCON3.1 RSVD
ADCCON3.0 RSVD
ocation
B
A
U
D
S
C
Y
I
Name
R
D
S
M
V
A
D
Description
The ADC interrupt bit (ADCI) is set by hardware at the end of a single ADC conversion cycle or at the
end of a DMA block conversion. ADCI is cleared by hardware when the PC vectors to the ADC Interrupt
Service Routine.
The DMA mode enable bit (DMA) is set by the user to enable a preconfigured ADC DMA mode operation.
A more detailed description of this mode is given in the ADC DMA Mode section.
The continuous conversion bit (CCONV) is set by the user to initiate the ADC into a continuous mode
of conversion. In this mode, the ADC starts converting based on the timing and channel configuration
already set up in the ADCCON SFRs; the ADC automatically starts another conversion once a previous
conversion has completed.
The single conversion bit (SCONV) is set to initiate a single conversion cycle. The SCONV bit is
automatically reset to “0” on completion of the single conversion cycle.
The channel selection bits (CS3–0) allow the user to program the ADC channel selection under
software control. When a conversion is initiated, the channel converted will be the one pointed to by
these channel selection bits. In DMA mode, the channel selection is derived from the channel ID
written to the external memory.
CS3 CS2 CS1 CS0 CH#
0
0
0
0
0
0
0
0
1
1
All other combinations reserved.
Description
The ADC busy status bit (BUSY) is a read-only status bit that is set during a valid ADC conversion
or calibration cycle. BUSY is automatically cleared by the core at the end of conversion or calibration.
ADCCON3.0–3.6 are reserved (RSVD) for internal use. These bits will read as “0” and should only
be written as “0” by user software.
D8H
00H
F5H
00H
0
0
0
0
1
1
1
1
0
1
C
R
C
S
O
V
D
N
0
0
1
1
0
0
1
1
0
1
V
Table IV. ADCCON2 SFR Bit Designations
Table V. ADCCON3 SFR Bit Designations
0
1
0
1
0
1
0
1
0
1
R
S
0
1
2
3
4
5
6
7
Temp Sensor
DMA STOP
S
C
V
O
D
N
V
–14–
R
S
C
V
S
D
3
R
S
C
V
S
D
2
R
C
S
V
S
D
1
R
C
S
S
V
0
D
REV. E