C8051F700DK Silicon Laboratories Inc, C8051F700DK Datasheet - Page 227

• Manufacturer Part Number: C8051F700DK
• Description: DEV KIT FOR C8051F700
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F700DK

• Contents: Board, Cables, CD, Debugger, Power Supply
• Processor To Be Evaluated: C8051F7x
• Processor Series: C8051F7xx
• Interface Type: USB
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F7xx
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1635

SFR Definition 30.2. SMB0CN: SMBus Control
SFR Address = 0xC0; SFR Page = All Pages; Bit-Addressable
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
ARBLOST SMBus Arbitration Lost
TXMODE SMBus Transmit Mode
MASTER SMBus Master/Slave
ACKRQ
Name
MASTER
STO
ACK
STA
SI
R
7
0
Indicator. This read-only bit
indicates when the SMBus is
operating as a master.
Indicator. This read-only bit
indicates when the SMBus is
operating as a transmitter.
SMBus Start Flag.
SMBus Stop Flag.
SMBus Acknowledge
Request.
Indicator.
SMBus Acknowledge.
SMBus Interrupt Flag.
This bit is set by hardware
under the conditions listed in
Table 15.3. SI must be cleared
by software. While SI is set,
SCL is held low and the
SMBus is stalled.
TXMODE
R
6
0
Description
R/W
STA
5
0
STO
R/W
Rev. 1.0
0: SMBus operating in
slave mode.
1: SMBus operating in
master mode.
0: SMBus in Receiver
Mode.
1: SMBus in Transmitter
Mode.
0: No Start or repeated
Start detected.
1: Start or repeated Start
detected.
0: No Stop condition
detected.
1: Stop condition detected
(if in Slave Mode) or pend-
ing (if in Master Mode).
0: No Ack requested
1: ACK requested
0: No arbitration error.
1: Arbitration Lost
0: NACK received.
1: ACK received.
0: No interrupt pending
1
4
0
:
Interrupt Pending
ACKRQ
Read
R
3
0
ARBLOST
C8051F70x/71x
R
2
0
N/A
N/A
0: No Start generated.
1: When Configured as a
Master, initiates a START
or repeated START.
0: No STOP condition is
transmitted.
1: When configured as a
Master, causes a STOP
condition to be transmit-
ted after the next ACK
cycle.
Cleared by Hardware.
N/A
N/A
0: Send NACK
1: Send ACK
0: Clear interrupt, and initi-
ate next state machine
event.
1: Force interrupt.
ACK
R/W
1
0
Write
R/W
SI
0
0
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