C8051F700DK Silicon Laboratories Inc, C8051F700DK Datasheet - Page 59
![DEV KIT FOR C8051F700](/photos/9/23/92340/c8051f700dk_sml.jpg)
C8051F700DK
Manufacturer Part Number
C8051F700DK
Description
DEV KIT FOR C8051F700
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets
1.C8051F700-TB.pdf
(1 pages)
2.C8051F700-TB.pdf
(306 pages)
3.C8051F700-TB.pdf
(18 pages)
Specifications of C8051F700DK
Contents
Board, Cables, CD, Debugger, Power Supply
Processor To Be Evaluated
C8051F7x
Processor Series
C8051F7xx
Interface Type
USB
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F7xx
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1635
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SFR Definition 10.1. ADC0CF: ADC0 Configuration
SFR Address = 0xBC; SFR Page = F
Name
Reset
Bit
7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Period Bits.
Type
2
1
0
Bit
AMP0GN0 ADC Gain Control Bit.
AD0LJST
AD08BE
Name
7
1
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC4–0. SAR Conversion clock
requirements are given in the ADC specification table.
ADC0 Left Justify Select.
0: Data in ADC0H:ADC0L registers are right-justified.
1: Data in ADC0H:ADC0L registers are left-justified.
Note: The AD0LJST bit is only valid for 10-bit mode (AD08BE = 0).
8-Bit Mode Enable.
0: ADC operates in 10-bit mode (normal).
1: ADC operates in 8-bit mode.
Note: When AD08BE is set to 1, the AD0LJST bit is ignored.
0: Gain = 0.5
1: Gain = 1
AD0SC
6
1
=
AD0SC[4:0]
SYSCLK
---------------------- - 1
CLK
R/W
5
1
SAR
–
Rev. 1.0
4
1
Function
3
1
AD0LJST
R/W
C8051F70x/71x
2
0
AD08BE
R/W
1
0
AMP0GN0
R/W
0
1
59
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