C8051F700DK Silicon Laboratories Inc, C8051F700DK Datasheet - Page 38
![DEV KIT FOR C8051F700](/photos/9/23/92340/c8051f700dk_sml.jpg)
C8051F700DK
Manufacturer Part Number
C8051F700DK
Description
DEV KIT FOR C8051F700
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets
1.C8051F700-TB.pdf
(1 pages)
2.C8051F700-TB.pdf
(306 pages)
3.C8051F700-TB.pdf
(18 pages)
Specifications of C8051F700DK
Contents
Board, Cables, CD, Debugger, Power Supply
Processor To Be Evaluated
C8051F7x
Processor Series
C8051F7xx
Interface Type
USB
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F7xx
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1635
- Current page: 38 of 306
- Download datasheet (2Mb)
C8051F70x/71x
38
Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
pad is to be 60 m minimum, all the way around the pad.
solder paste release.
Components.
Dimension
C1
C2
E
X
Y
Table 4.2. TQFP-64 PCB Land Pattern Dimensions
Figure 4.2. TQFP-64 PCB Land Pattern
Rev. 1.0
11.30
11.30
0.20
1.40
Min
0.50 BSC
11.40
11.40
Max
0.30
1.50
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