C8051T610DK Silicon Laboratories Inc, C8051T610DK Datasheet - Page 30
C8051T610DK
Manufacturer Part Number
C8051T610DK
Description
KIT DEV FOR C8051T61X MCU'S
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051T610DK
Contents
Board, daughter boards, power adapter, cables, documentation and software
Processor To Be Evaluated
C8051T61x
Interface Type
USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051T610
For Use With
336-1507 - DAUGHTER BOARD T610 24QFN SOCKET336-1506 - DAUGHTER BOARD T610 28QFN SOCKET336-1505 - DAUGHT BOARD T610 32TQFP SOCKET
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1443
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C8051T610/1/2/3/4/5/6/7
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Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
Dimension
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
5. The stencil thickness should be 0.125mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A 2x2 array of 1.10mm x 1.10mm openings on a 1.30mm pitch should be used for the center
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for
C1
C2
X1
E
mask and the metal pad is to be 60m minimum, all the way around the pad.
to assure good solder paste release.
pad.
Small Body Components.
Figure 6.2. QFN-24 Recommended PCB Land Pattern
Table 6.2. QFN-24 PCB Land Pattern Dimesions
3.90
3.90
0.20
Min
0.50 BSC
Max
4.00
4.00
0.30
Rev 1.0
Dimension
X2
Y1
Y2
2.70
0.65
2.70
Min
Max
2.80
0.75
2.80
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