C8051T610DK Silicon Laboratories Inc, C8051T610DK Datasheet - Page 90

• Manufacturer Part Number: C8051T610DK
• Description: KIT DEV FOR C8051T61X MCU'S
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051T610DK

• Contents: Board, daughter boards, power adapter, cables, documentation and software
• Processor To Be Evaluated: C8051T61x
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051T610
• For Use With: 336-1507 - DAUGHTER BOARD T610 24QFN SOCKET336-1506 - DAUGHTER BOARD T610 28QFN SOCKET336-1505 - DAUGHT BOARD T610 32TQFP SOCKET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1443

C8051T610/1/2/3/4/5/6/7
SFR Definition 16.3. EIE1: Extended Interrupt Enable 1
SFR Address = 0xE6
90
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
EWADC0 Enable Window Comparison ADC0 Interrupt.
Reserved Reserved. Must Write 0.
EADC0
ESMB0
EPCA0
Name
ECP1
ECP0
ET3
R/W
ET3
7
0
Enable Timer 3 Interrupt.
This bit sets the masking of the Timer 3 interrupt.
0: Disable Timer 3 interrupts.
1: Enable interrupt requests generated by the TF3L or TF3H flags.
Enable Comparator1 (CP1) Interrupt.
This bit sets the masking of the CP1 interrupt.
0: Disable CP1 interrupts.
1: Enable interrupt requests generated by the CP1RIF or CP1FIF flags.
Enable Comparator0 (CP0) Interrupt.
This bit sets the masking of the CP0 interrupt.
0: Disable CP0 interrupts.
1: Enable interrupt requests generated by the CP0RIF or CP0FIF flags.
Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT).
Enable SMBus (SMB0) Interrupt.
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests generated by SMB0.
ECP1
R/W
6
0
ECP0
R/W
5
0
EPCA0
R/W
Rev 1.0
4
0
Function
EADC0
R/W
3
0
EWADC0
R/W
2
0
Reserved
R/W
1
0
ESMB0
R/W
0
0