MC56F8367EVME Freescale Semiconductor, MC56F8367EVME Datasheet - Page 103

• Manufacturer Part Number: MC56F8367EVME
• Description: EVAL BOARD FOR MC56F83X
• Manufacturer: Freescale Semiconductor
• Type: DSPr

Specifications of MC56F8367EVME

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC56F8145-67 and MC56F8345-67
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: 56800/E
• Core Sub-architecture: 56800/E
• Silicon Core Number: MC56F
• Silicon Family Name: MC56F83xx
• Rohs Compliant: Yes
• For Use With/related Products: MC56F83x5, MC56F83x6, MC56F83x7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

occur if a fast interrupt vector is set to any other priority. Fast interrupts automatically become the
highest-priority level 2 interrupt, regardless of their location in the interrupt table, prior to being declared
as fast interrupt. Fast interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each
IRQ, refer to
5.6.13
5.6.13.1
The lower 16 bits of the vector address are used for Fast Interrupt 0. This register is combined with
FIVAH0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.
5.6.14
5.6.14.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.14.2
The upper five bits of the vector address are used for Fast Interrupt 0. This register is combined with
FIVAL0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.
5.6.15
5.6.15.1
This bit field is reserved or not implemented. It is read as 0, but cannot be modified by writing.
Freescale Semiconductor
Preliminary
Base + $C
Base + $D
Base + $E
RESET
RESET
RESET
Write
Write
Write
Read
Read
Read
Fast Interrupt 0 Vector Address Low Register (FIVAL0)
Fast Interrupt 0 Vector Address High Register (FIVAH0)
Fast Interrupt 1 Match Register (FIM1)
Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15–0
Figure 5-16 Fast Interrupt 0 Vector Address High Register (FIVAH0)
Reserved—Bits 15–5
Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0
Reserved—Bits 15–7
Figure 5-15 Fast Interrupt 0 Vector Address Low Register (FIVAL0)
Table
15
15
15
0
0
0
0
0
4-5.
Figure 5-17 Fast Interrupt 1 Match Register (FIM1)
14
14
14
0
0
0
0
0
13
13
13
0
0
0
0
0
12
12
12
0
0
0
0
0
56F8367 Technical Data, Rev. 8
11
11
11
0
0
0
0
0
FAST INTERRUPT 0 VECTOR ADDRESS LOW
10
10
10
0
0
0
0
0
9
0
9
0
0
9
0
0
8
0
8
0
0
8
0
0
7
7
7
0
0
0
0
0
6
6
6
0
0
0
0
5
0
5
0
0
5
0
FAST INTERRUPT 1
4
4
4
0
0
0
FAST INTERRUPT 0 VECTOR
3
3
3
0
0
0
ADDRESS HIGH
2
0
2
0
2
0
Register Descriptions
1
0
1
0
1
0
0
0
0
0
0
0
103