MC56F8367EVME Freescale Semiconductor, MC56F8367EVME Datasheet - Page 147

• Manufacturer Part Number: MC56F8367EVME
• Description: EVAL BOARD FOR MC56F83X
• Manufacturer: Freescale Semiconductor
• Type: DSPr

Specifications of MC56F8367EVME

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC56F8145-67 and MC56F8345-67
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: 56800/E
• Core Sub-architecture: 56800/E
• Silicon Core Number: MC56F
• Silicon Family Name: MC56F83xx
• Rohs Compliant: Yes
• For Use With/related Products: MC56F83x5, MC56F83x6, MC56F83x7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.5 External Clock Operation Timing
10.6 Phase Locked Loop Timing
Freescale Semiconductor
Preliminary
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
2. ZCLK may not exceed 60MHz. For additional information on ZCLK and (f
3. This is the minimum time required after the PLL set up is changed to ensure reliable operation.
1. Parameters listed are guaranteed by design.
2. See
3. The high or low pulse width must be no smaller than 8.0ns or the chip will not function.
4. External clock input rise time is measured from 10% to 90%.
5. External clock input fall time is measured from 90% to 10%.
External reference crystal frequency for the PLL
PLL output frequency
PLL stabilization time
Frequency of operation (external clock driver)
Clock Pulse Width
External clock input rise time
External clock input fall time
correctly. The PLL is optimized for 8MHz input crystal.
the 56F8300 Peripheral User Manual.
External
Note: The midpoint is V
Clock
Figure 10-3
Table 10-13 External Clock Operation Timing Requirements
Characteristic
Characteristic
for details on using the recommended connection of an external clock driver.
3
10%
50%
90%
2
3
-40° to +125°C
(f
OUT
t
PW
IL
)
5
4
+ (V
Figure 10-3 External Clock Timing
IH
– V
IL
Table 10-14 PLL Timing
56F8367 Technical Data, Rev. 8
)/2.
2
t
PW
1
f
t
t
t
Symbol
osc
PW
rise
fall
Symbol
f
t
f
osc
plls
op
Min
3.0
—
—
0
Min
OUT
160
t
—
fall
4
/2), please refer to the OCCS chapter in
Typ
—
—
—
—
Typ
—
8
1
External Clock Operation Timing
t
rise
Max
Max
120
260
8.4
10
10
—
10
1
10%
50%
90%
MHz
V
V
Unit
MHz
MHz
Unit
ns
ns
ns
ms
IH
IL
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