EZ80F920200ZCO Zilog, EZ80F920200ZCO Datasheet - Page 24
EZ80F920200ZCO
Manufacturer Part Number
EZ80F920200ZCO
Description
KIT DEV FOR EZ80F92 W/C-COMPILER
Manufacturer
Zilog
Series
eZ80 Acclaim!®r
Type
MCUr
Datasheet
1.EZ80F920200ZCO.pdf
(90 pages)
Specifications of EZ80F920200ZCO
Contents
2 Primary Boards, Hardware, Software and Documentation
For Use With/related Products
eZ80F92
For Use With
269-4661 - KIT ACC ETHERNET SMART CABLE
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3162
EZ80F920200ZCO
EZ80F920200ZCO
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14
Operational Description
Pin #
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
Notes:
1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from
2. The Power and Ground nets are connected directly to the eZ80F92 device.
3. External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10pF
eZ80F92 Development Kit
User Manual
this table. The entire interface is represented in the eZ80F92 Module Schematics
through
to satisfy the timing requirements for the eZ80
either V
reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in
the eZ80F91’s Peripheral Power-Down Register.
DD
64.
Symbol
CS0
CS1
CS2
D0
D1
D2
D3
D4
D5
GND
D7
D6
MREQ
IORQ
GND
Peripheral Bus Connector Identification—JP1* (Continued)
or GND, depending on their inactive levels to reduce power consumption and to
Table 2. eZ80
Signal Direction
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Input
Input
Input
®
Development Platform
PRELIMINARY
®
CPU. All unused inputs should be pulled to
Active Level
Low
Low
Low
Low
Low
eZ80F92 Signal
UM013904-0203
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
on pages 62
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