EZ80F920200ZCO Zilog, EZ80F920200ZCO Datasheet - Page 69

• Manufacturer Part Number: EZ80F920200ZCO
• Description: KIT DEV FOR EZ80F92 W/C-COMPILER
• Manufacturer: Zilog
• Series: eZ80 Acclaim!®r
• Type: MCUr

Specifications of EZ80F920200ZCO

• Contents: 2 Primary Boards, Hardware, Software and Documentation
• For Use With/related Products: eZ80F92
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3162; EZ80F920200ZCO

Schematic Diagrams
UM013904-0203
eZ80
DO NOT USE J6_17 AND J6_35
9VDC
-MOD_DIS
PC6_DCD1
PC5_DSR1
PC4_DTR1
PC1_RXD1
PC3_CTS1
PC2_RTS1
PC0_TXD1
-MWAIT
EM_D0
EM_D7
EM_D6
EM_D5
EM_D4
EM_D3
EM_D2
EM_D1
PC7_RI1
-BUSACK
GND
SCL
SDA
3
-NMI
9V_DC
U8A
TC74LVT125
®
-RD
-MEMRQ
-CS0
-CS2
Figures 17 through 21 diagram the layout of the eZ80
VDD
GND
GND
VDD
GND
Development Platform
-CS3
VCC
GND
GND
2
GND
-RESET
GND
VDD
A0
A2
A4
A6
A8
A10
A12
A14
A16
A18
A20
A22
D0
D2
D4
D6
GND
VDD
R5
1K
J6
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
Header 30x2
J8
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
Header 30x2
TVCC_RESETn
3
GND
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
2
4
6
8
2
4
6
8
U9A
VDD
PB1_T1_I
PB0_T0_I
GND
GND
PB7_MOSI
PB6_MISO
PB5_T5_O
PB4_T4_O
PB3_SCK
PB2_SS
A1
A3
A5
A7
A9
A11
A13
A15
A17
A19
A21
A23
PHI
GND
D1
D3
D5
D7
GND
TDI
TDO
TCK
VDD
ID_2
ID_1
ID_0
GND
TC74LVC08
1
2
GND
GND
VDD
GND
-CS1
-CS_EX
-IORQ
GND
PD7_RI0
PD6_DCD0
PD5_DSR0
PD4_DTR0
PD3_CTS0
PD2_RTS0
PD1_RXD0
PD0_TXD0
PB2_SS
PB1_T1_I
PB0_T0_I
ID_2
ID_1
ID_0
-CON_DIS
-WR
INSTRD
-BUSREQ
PHI
VDD
1
3
5
7
9
11
13
P1
-DIS_ETH
Figure 17. eZ80
con 7x2
VDD
10
12
14
R3
10K
2
4
6
8
VDD
GND
-RESET
R1
10K
-DIS_ETH
-M_WR
-BUSACK
TRIGOUT
MA6
MA10
MA8
MA13
MA15
MA18
MA19
MA2
MA11
MA4
MA5
MA21
MA22
-M_CS0
-M_CS2
MD1
MD3
MD5
MD7
-M_MEMRQ
PB7_MOSI
PB5_T5_O
PB3_SCK
PB1_T1_I
PC6_DCD1
PC4_DTR1
PC2_RTS1
PC0_TXD1
PD6_DCD0
PD5_DSR0
PD3_CTS0
PD1_RXD0
TDO
TCK
RTC_VDD
SCL
SDA
-FLASHWE
-M_CS3
-RESET
HALT_SLP
PRSTn
GND
TMS
GND
GND
GND
GND
VDD
VDD
J4
1
3
5
Header 3x2
ZDI
INTERFACE
VDD
2
4
6
R4
10K
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Header 25x2
JP2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Header 25x2
®
VDD
RX
TX
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Development Platform Schematic Diagram, #1 of 5
1
1
2
4
6
8
2
4
6
8
PRSTn
D2
D4
1
1
TCK
TDI
VDD
GND
VDD
GND
PC5_DSR1
PC3_CTS1
PC1_RXD1
PD7_RI0
GND
PD4_DTR0
PD2_RTS0
PD0_TXD0
GND
GND
D1
D3
PB6_MISO
PB4_T4_O
PB2_SS
PB0_T0_I
PC7_RI1
TRIGOUT
-DIS_IRDA
R19
10K
2
2
®
-DIS_FL
-M_IORQ
-M_RD
INSTRD
-BUSREQ
M_PHI
-MWAIT
-NMI
DCD
MA0
MA3
MA7
MA9
MA14
MA16
MA1
MA12
MA20
MA17
MA23
-M_CS1
MD0
MD2
MD4
MD6
TDI
TMS
DTR
Development Platform.
2
2
PRELIMINARY
-DIS_FL
M_TIP
M_RING
-MRESET
R8
R9
VDD
R20
R21
R2
10K
0
0
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MA14
MA15
MA16
MA17
MA18
MA19
MA20
MA21
MA22
MA23
GND
0
0
M_TIP
M_RING
-MRESET
GND
11
13
15
17
19
11
13
15
17
19
11
13
15
17
19
2
4
6
8
1
2
4
6
8
1
2
4
6
8
1
1
2
U1
74LVC244A
U3
74LVC244A
U5
74LVC244A
A1
A2
A3
A4
A5
A6
A7
A8
1OE
2OE
A1
A2
A3
A4
A5
A6
A7
A8
1OE
2OE
A1
A2
A3
A4
A5
A6
A7
A8
1OE
2OE
1
2
3
4
5
6
7
8
9
J5
HEADER 2
J9
HEADER 9
MODEM CONNECTORS
VCC
GND
VCC
GND
VCC
GND
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
18
16
14
12
9
7
5
3
20
10
18
16
14
12
9
7
5
3
20
10
18
16
14
12
9
7
5
3
20
10
HEADER 32
J1
VDD
GND
VDD
GND
VDD
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A[23:0]
MODEM's
AGND
VCC
PC4_DTR1
PC6_DCD1
PC3_CTS1
PC5_DSR1
PC7_RI1
PC0_TXD1
PC1_RXD1
PC2_RTS1
GND
C30
0.1uF
C31
0.1uF
C33
0.1uF
-MOD_DIS
A[23:0]
J2
HEADER 2
HEADER 2
J7
1
2
1
2
VCC
VDD
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
-M_RD
-L_RD
GND
GND
VCC
VDD
GND
-FLASHWE
GND
J12
1
2
3
Header 3
-DIS_IRDA
19
2
3
4
5
6
7
8
9
1
-M_IORQ
-M_MEMRQ
-M_CS0
-M_CS1
-M_CS2
-M_WR
-M_RD
-M_CS3
M_PHI
U7
74LVC245/SO
A0
A1
A2
A3
A4
A5
A6
A7
DIR
OE
VCC
VDD
GND
SCL
VCC
GND
GND
B0
B1
B2
B3
B4
B5
B6
B7
10
11
13
2
3
4
5
6
7
8
9
1
GND
18
17
16
15
14
13
12
11
20
10
U21
74LVC827/SO
eZ80F92 Development Kit
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
OE1
OE2
GND
1
2
6
7
VDD
VCC
GND
Y10
U2
AT24C128
A0
A1
SCL
WP
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
D0
D1
D2
D3
D4
D5
D6
D7
GND
SDA
VCC
23
22
21
20
19
18
17
16
15
14
24
12
C1
0.1uF
NC
GND
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
5
8
4
3
Schematic Diagrams
D[7:0]
-CS0
-CS1
-CS2
-IORQ
-MEMRQ
-WR
-RD
-CS3
PHI
VDD
SDA
VDD
User Manual
D[7:0]
C34
0.1uF
MD[7:0]
59