YR0K42378FC000BA Renesas Electronics America, YR0K42378FC000BA Datasheet - Page 265

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YR0K42378FC000BA

Manufacturer Part Number
YR0K42378FC000BA
Description
KIT EVAL FOR H8S/2378
Manufacturer
Renesas Electronics America
Series
H8®r
Type
MCUr
Datasheet

Specifications of YR0K42378FC000BA

Contents
Board
For Use With/related Products
H8S/2378
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
If a row address hold time or read access time is necessary, making a setting in bits RCD1 and
RCD0 in DRACCR allows from one to three T
maintained, to be inserted between the T
cycle, in which the column address is output. Use the setting that gives the optimum row address
signal hold time relative to the falling edge of the RAS signal according to the DRAM connected
and the operating frequency of this LSI. Figure 6.24 shows an example of the timing when one T
state is set.
Read
Write
Note: n = 2 to 5
Figure 6.24 Example of Timing with One Row Address Output Maintenance State
φ
Address bus
RASn (CSn)
UCAS, LCAS
WE (HWR)
OE (RD)
Data bus
WE (HWR)
OE (RD)
Data bus
T
p
(RAST = 0, CAST = 0)
Row address
r
cycle, in which the RAS signal goes low, and the T
T
r
rw
states, in which row address output is
Rev.7.00 Mar. 18, 2009 page 197 of 1136
T
rw
Section 6 Bus Controller (BSC)
High
High
T
Column address
c1
REJ09B0109-0700
T
c2
c1
rw

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