HS7729KCI01H Renesas Electronics America, HS7729KCI01H Datasheet - Page 105

• Manufacturer Part Number: HS7729KCI01H
• Description: ON CHIP DEBUG EMULATOR
• Manufacturer: Renesas Electronics America
• Type: In Circuit Debuggerr

Specifications of HS7729KCI01H

• Contents: E10A-LITE, Cable and CD-ROM
• For Use With/related Products: SH7729
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.19.3
The MCU, which has an MMU, translates internal addresses (virtual addresses) to actual memory
addresses (physical addresses). Address translation is performed according to the address
translation table (translation look-aside buffer: TLB) in the MCU. The MMU operates during
command input wait state as well as during user program execution. When a command for
memory access is executed while the MMU address translation function is enabled, the address
translated by the MMU is accessed. If the specified address is not within the TLB, a TLB miss
occurs, and the TLB must be updated by the user program.
The emulator has address translation functions according to the VP_MAP tables. The VP_MAP
tables are the address translation tables for the emulator created with the VPMAP_SET command.
The following shows an example of how to use the VP_MAP tables.
Example:
1. Create VP_MAP tables for translating virtual addresses H'10000 to H'10FFF to physical
2. Then, enable the VP_MAP tables. (When the tables are disabled, addresses are not translated.)
addresses H'4000000 to H'4000FFF and virtual addresses H'11000 to H'11FFF to physical
addresses H'0 to H'FFF.
>vs 10000 10FFF 4000000 (RET)
>vs 11000 11FFF 0 (RET)
>vd (RET)
<VADDR_TOP>
00010000
00011000
DISABLE
>ve ;enable (RET)
>vd (RET)
<VADDR_TOP>
00010000
00011000
ENABLE
Here, virtual addresses correspond to physical addresses as shown in figure 3.58.
VP_MAP Translation
<VADDR_END>
00010FFF
00011FFF
<VADDR_END>
00010FFF
00011FFF
<PADDR_TOP>
04000000
00000000
<PADDR_TOP>
04000000
00000000
Rev. 2.0, 01/01, page 79 of 216