HS7729KCI01H Renesas Electronics America, HS7729KCI01H Datasheet - Page 223

• Manufacturer Part Number: HS7729KCI01H
• Description: ON CHIP DEBUG EMULATOR
• Manufacturer: Renesas Electronics America
• Type: In Circuit Debuggerr

Specifications of HS7729KCI01H

• Contents: E10A-LITE, Cable and CD-ROM
• For Use With/related Products: SH7729
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Notes: 1. The memory must not be accessed or modified in sleep mode.
Note: Do not break the user program when the /RESETP, /RESETM, /BREQ, and /WAIT
Low-Power Mode (Sleep, Standby, and Module Standby)
For low-power consumption, the SH7729 and SH7709A have sleep, standby, and module
standby modes.
The sleep and standby modes are switched using the SLEEP instruction. When the emulator is
used, only the sleep mode can be cleared with either the normal clearing function or with the
[Stop] button. Note that if a command has been entered in standby mode or module standby
mode, no commands can be used from the emulator. The states cannot be canceled by the
[Stop] button.
RESET Signals (/RESETP and /RESETM)
The SH7729 and SH7709A RESET signals (/RESETP and /RESETM) are only valid during
emulation started with clicking the GO or STEP-type button. If these signals are input from
the user system in command input wait state, they are not sent to the SH7729 or SH7709A.
Direct Memory Access Controller (DMAC)
The DMAC operates even when the emulator is used. When a data transfer request is
generated, the DMAC executes DMA transfer.
Internal I/O Register
In the emulator, the internal I/O can be accessed from the [I/O Registers] window. However,
pay attention when accessing the SDMR register of the bus-state controller. Before accessing
the SDMR register, specify addresses to be accessed in the I/O-register definition file
(SH7729.IO or SH7709A.IO) and then activate the HDI. For the I/O-register definition file,
refer to the Hitachi Debugging Interface User’s Manual.
Memory Access during Emulation
When a memory is accessed from the memory window, etc. during user program execution,
the user program is resumed after it has stopped in the E10A emulator to access the memory.
Therefore, realtime emulation cannot be performed.
The stopping time of the user program is as follows:
2. When the [Stop] button is clicked in sleep mode, a break does not occur immediately
signals are being low. A TIMEOUT error will occur. If the /BREQ and /WAIT
signals are fixed to low during break, a TIMEOUT error will occur at memory
access.
after executing the SLEEP instruction. The number of instructions to be proceeded
differs according to the emulator environment or operating frequency of the chip. It is
about 150 instructions when the Pentium III 500-MHz PC is used and the CPU clock is
25 MHz.
Rev. 2.0, 01/01, page 197 of 216