ST92F150-EMU2 STMicroelectronics, ST92F150-EMU2 Datasheet - Page 175

• Manufacturer Part Number: ST92F150-EMU2
• Description: BOARD EMULATOR FOR ST9 SERIES
• Manufacturer: STMicroelectronics
• Series: ST9-EMU2r
• Type: Microcontrollerr

Specifications of ST92F150-EMU2

• Contents: ST9 Visual Debug IDE, ST9 HDS2V2 Mainboard, Probe, Sockets, Adapters, Power Supply,Cables & Documentation
• For Use With/related Products: ST9 MCUs
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-3101

EXTENDED FUNCTION TIMER (Cont’d)
10.3.3.5 Forced Compare Mode
In this section i may represent 1 or 2.
The following bits of the CR1 register are used:
When the FOLV1 bit is set, the OLVL1 bit is copied
to the OCMP1 pin if PWM and OPM are both
cleared.
When the FOLV2 bit is set, the OLVL2 bit is copied
to the OCMP2 pin.
The OLVLi bit has to be toggled in order to toggle
the OCMPi pin when it is enabled (OCiE bit=1).
Notes:
– The OCFi bit is not set when FOLVi is set, and
– The OCFi bit can be set if OCiR = Counter and
– The Input Capture function works in Forced com-
10.3.3.6 One Pulse Mode
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
The one pulse mode uses the Input Capture1
function and the Output Compare1 function.
Procedure
To use one pulse mode, select the following in the
the CR1 register:
– Using the OLVL1 bit, select the level to be ap-
– Using the OLVL2 bit, select the level to be ap-
– Select the edge of the active transition on the
And select the following in the CR2 register:
– Set the OC1E bit, the OCMP1 pin is then dedi-
– Set the OPM bit.
– Select the timer clock CC[1:0] (see
thus no interrupt request is generated.
an interrupt can be generated if enabled. This
can be avoided by writing in the OCiHR register.
The output compare function is inhibited till
OCiLR is also written.
pare mode. To disable it, read the ICiHR register.
Input capture will be inhibited till ICiLR is read.
plied to the OCMP1 pin after the pulse.
plied to the OCMP1 pin during the pulse.
ICAP1 pin with the IEDG1 bit.
cated to the Output Compare 1 function.
FOLV2 FOLV1 OLVL2
Table
OLVL1
36).
Load the OC1R register with the value corre-
sponding to the length of the pulse (see the formu-
la in
Then, on a valid event on the ICAP1 pin, the coun-
ter is initialized to FFFCh and OLVL2 bit is loaded
on the OCMP1 pin. When the value of the counter
is equal to the value of the contents of the OC1R
register, the OLVL1 bit is output on the OCMP1
pin, (See
Notes:
– The OCF1 bit cannot be set by hardware in one
– The ICF1 bit is set when an active edge occurs
– When the Pulse Width Modulation (PWM) and
– When One Pulse Mode (OPM) and Forced Com-
– Forced Compare 2 mode works in OPM
– Input Capture 2 function works in OPM
– When OC1R = FFFCh in OPM, then a pulse of
– If IC1HR register is read in OPM before an active
pulse mode but the OCF2 bit can generate an
Output Compare interrupt.
and can generate an interrupt if the ICIE bit is set
or ICIE is reset and IC1IE is set. The IC1R regis-
ter will have the value FFFCh.
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
pare 1 mode (FOLV1) bits are set then OPM is
the active mode
width FFFCh is generated
edge of ICAP1, then OPM is inhibited till IC1LR
is also read.
Section
EXTENDED FUNCTION TIMER (EFT)
event occurs
on ICAP1
Counter
= OC1R
When
Figure
When
10.3.3.7).
99).
One pulse mode cycle
OCMP1 = OLVL2
OCMP1 = OLVL1
Counter is
initialized
to FFFCh
175/429
9