ST92F150-EMU2 STMicroelectronics, ST92F150-EMU2 Datasheet - Page 184

• Manufacturer Part Number: ST92F150-EMU2
• Description: BOARD EMULATOR FOR ST9 SERIES
• Manufacturer: STMicroelectronics
• Series: ST9-EMU2r
• Type: Microcontrollerr

Specifications of ST92F150-EMU2

• Contents: ST9 Visual Debug IDE, ST9 HDS2V2 Mainboard, Probe, Sockets, Adapters, Power Supply,Cables & Documentation
• For Use With/related Products: ST9 MCUs
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-3101

EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
CONTROL REGISTER 1 (CR1)
R252 - Read/Write
Register Page: 28
Reset Value: 0000 0000 (00h)
Bit 7 = ICIE Input Capture Interrupt Enable.
0: Interrupt enabling depends on the IC1IE and
1: An interrupt is generated whenever the ICF1 or
Bit 6 = OCIE Output Compare Interrupt Enable.
0: Interrupt generation depends on the OC1IE and
1: An interrupt is generated whenever the OCF1 or
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
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ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
9
7
IC2IE bits in the CR3 register.
ICF2 bit in the SR register is set. The IC1IE and
IC2IE bits in the CR3 register do not have any
effect in this case.
OC2IE bits in the CR3 register.
OCF2 bit in the SR register is set. The OC1IE
and OC2IE bits in the CR3 rgister do not have
any effect in this case.
bit of the SR register is set.
0
Bit 4 = FOLV2 Forced Output Compare 2.
0: No effect.
1: Forces the OLVL2 bit to be copied to the
Bit 3 = FOLV1 Forced Output Compare 1.
0: No effect.
1: Forces OLVL1 to be copied to the OCMP1 pin.
Bit 2 = OLVL2 Output Level 2.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R reg-
ister and OC2E is set in the CR2 register. This val-
ue is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.
Bit 1 = IEDG1 Input Edge 1.
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 = OLVL1 Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
OCMP2 pin.