ST92F150-EMU2 STMicroelectronics, ST92F150-EMU2 Datasheet - Page 416

• Manufacturer Part Number: ST92F150-EMU2
• Description: BOARD EMULATOR FOR ST9 SERIES
• Manufacturer: STMicroelectronics
• Series: ST9-EMU2r
• Type: Microcontrollerr

Specifications of ST92F150-EMU2

• Contents: ST9 Visual Debug IDE, ST9 HDS2V2 Mainboard, Probe, Sockets, Adapters, Power Supply,Cables & Documentation
• For Use With/related Products: ST9 MCUs
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-3101

ST92F124/F150/F250 - KNOWN LIMITATIONS
KNOWN LIMITATIONS (Cont’d)
Figure 3. Workaround 1 in Assembler
We can assume a time quantum number between
8 and 25. The worst case is when the baud rate
prescaler is 0 (BRP=0) and the time quantum is 8,
ie. TS1+TS2=5. This means a CPU frequency of
8MHz and 1 Mbits/sec for the CAN communica-
tion. In this case the minimum time between the
end of the acknowledge and the critical period is
52 CPU cycles (48 for the 6 bit times + 4 for the
(PROP SEG + T
code timing, we need less than 22 cycles from the
time we see the dominant state to the time we per-
form the FIFO release (one full loop + the actual
release) therefore the application will never re-
lease the FIFO at the critical time when this work-
around is implemented.
Timing analysis
- Time spent in the workaround
Inside a CAN frame, the longest period that the Rx
pin stays in recessive state is 5 bits. At the end of
the frame, the time between the acknowledge
dominant bit and the end of reception (signaled by
REC bit status) is 8T
i m u m t i m e s p e n t i n t h e w o r k a r o u n d i s :
8T
8T
416/429
1
asm (“
_whileloop: btjf r1.5, _release /* REC bit of CMSR register
_release:
“);
CANbit
CANbit
+68T
spp #48
ld
and
cp
jxnz
pushw RR232
srp
btjf
popw
+T
loop
CPU
+T
r0, R244
r0, #3
r0, #2
_release
#31
r12.3, _whileloop /* RX bit of CDGR register
or R244, #32
RR232
Seg 1
.
test
). According to the previous
CANbit
+T
release
, therefore the max-
in this case or
/*
/* set CAN0_CTRL page
/* Use spp #36 for CAN1
/* For FIFO 0
/* NB: Replace R244 with R245 for FIFO 1
/*
/*
/* (JRNE instruction)
/* if FMP is not 2 then FIFO
/* release can be done
/* push working group
/* set group F as working group
/*
/* NB: Replace R244 with R245 for FIFO 1
/* restore previous working group
set RFOM bit of CRFR register
At low speed, this time could represent a long
delay for the application, therefore it makes sense
to evaluate how frequently this delay occurs.
In order to reach the critical FMP=2, the CAN node
needs to receive 2 messages without servicing
them. Then in order to reach the critical window,
the cell has to receive a third one and the applica-
tion has to release the mailbox at the same time, at
the end of the reception.
In the application, messages are not processed
only if either the interrupt are disabled or higher
level interrupts are being serviced.
Therefore if:
T
frame
the application will never wait in the workaround
T
interrupts with a level strictly higher than the CAN
interrupt level
T
disables the CAN interrupt (or all interrupts)
T
the beginning of the CAN interrupt and the actual
location of the workaround
IT higher level
IT higher level
IT disable
IT CAN
: This is the maximum duration between
: This is the longest time the application
: This the sum of the duration of all the
+ T
IT disable
Bytes/cycles
2/4
2/4
3/6
3/6
2/6
2/8 or 10
2/4
3/6 or 10 if jmp
3/6 or 10 if jmp
3/6
2/10
+ T
IT CAN
< 2 x T
CAN
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
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*/
*/