ST92F150-EMU2 STMicroelectronics, ST92F150-EMU2 Datasheet - Page 412

• Manufacturer Part Number: ST92F150-EMU2
• Description: BOARD EMULATOR FOR ST9 SERIES
• Manufacturer: STMicroelectronics
• Series: ST9-EMU2r
• Type: Microcontrollerr

Specifications of ST92F150-EMU2

• Contents: ST9 Visual Debug IDE, ST9 HDS2V2 Mainboard, Probe, Sockets, Adapters, Power Supply,Cables & Documentation
• For Use With/related Products: ST9 MCUs
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-3101

ST92F124/F150/F250 - KNOWN LIMITATIONS
KNOWN LIMITATIONS (Cont’d)
13.3.3 AF bit (acknowledge failure flag) in
transmitter mode (slave and master)
Description
The AF bit is cleared by reading the I2CSR2 reg-
ister. However, if read before the completion of the
transmission, the AF flag will be set again, thus
possibly generating a new interrupt.
Workaround
Software must ensure either that the SCL line is
back at 0 before reading the SR2 register, or be
able to correctly handle a second interrupt during
the 9th pulse of a transmitted byte.
13.3.4 BUSY flag in multimaster mode
Description
The BUSY flag is NOT updated when the interface
is disabled (PE=0). This can have consequences
when operating in Multimaster mode; i.e. a second
active I2C master commencing a transfer with an
unset BUSY bit can cause a conflict resulting in
lost data.
Workaround
Check that the I2C is not busy before enabling the
I2C Multimaster cell.
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13.3.5
multimaster mode
Description
In a Multimaster environment, when the interface
is configured in Master Receive mode it does not
perform arbitration during the reception of the Ac-
knowledge Bit. Mishandling of the ARLO bit from
the I2CSR2 register may occur when a second
master simultaneously requests the same data
from the same slave and the I2C master does not
acknowledge the data. The ARLO bit is then left at
0 instead of being set.
Workaround
None
13.3.6 BUSY flag gets cleared when BUS error
occurs
Description
BUSY bit gets cleared when the BUS error occurs
but the bus is actually BUSY (SCL line shows CLK
pulses). Contradictory, M/SL bit is unaffected on
BUS error
Workaround
If a Bus Error occurs, a Stop or a repeated Start
condition should be generated by the Master to re-
synchronize communication, get the transmission
acknowledged and the bus released for further
communication
ARLO
(arbitration
lost)
flag
in