ST92F150-EMU2 STMicroelectronics, ST92F150-EMU2 Datasheet - Page 212

• Manufacturer Part Number: ST92F150-EMU2
• Description: BOARD EMULATOR FOR ST9 SERIES
• Manufacturer: STMicroelectronics
• Series: ST9-EMU2r
• Type: Microcontrollerr

Specifications of ST92F150-EMU2

• Contents: ST9 Visual Debug IDE, ST9 HDS2V2 Mainboard, Probe, Sockets, Adapters, Power Supply,Cables & Documentation
• For Use With/related Products: ST9 MCUs
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-3101

MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
10.5 MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
10.5.1 Introduction
The Multiprotocol Serial Communications Inter-
face (SCI-M) offers full-duplex serial data ex-
change with a wide range of external equipment.
The SCI-M offers four operating modes: Asynchro-
nous, Asynchronous with synchronous clock, Seri-
al expansion and Synchronous.
10.5.2 Main Features
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■
■
■
Figure 106. SCI-M Block Diagram
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9
– 5, 6, 7, or 8 bit word length.
– Even, odd, or no parity generation and detec-
– 0, 1, 1.5, 2, 2.5, 3 stop bit generation.
– Complete status reporting capabilities.
– Line break generation and detection.
Full duplex synchronous and asynchronous
operation.
Transmit, receive, line status, and device
address interrupt generation.
Integral Baud Rate Generator capable of
dividing the input clock by any value from 2 to
2
16X data sampling clock for asynchronous
operation or the 1X clock for synchronous
operation.
Fully programmable serial interface:
16
tion.
-1 (16 bit word) and generating the internal
SOUT
TRANSMIT
REGISTER
REGISTER
TRANSMIT
BUFFER
SHIFT
RTS
CONTROLLER
SDS
DMA
TXCLK/CLKOUT RXCLK
ST9 CORE BUS
Frame Control
ALTERNATE
COMPARE
ADDRESS
REGISTER
and STATUS
FUNCTION
CLOCK and
GENERATOR
BAUD RATE
CONTROLLER
DMA
■
■
■
■
– Local loopback for communications link fault
– Auto-echo for communications link fault isola-
– High speed communication
– Possibility of hardware synchronization (RTS/
– Programmable polarity and stand-by level for
– Programmable active edge and stand-by level
– Programmable active levels of RTS/DCD sig-
– Full Loop-Back and Auto-Echo modes for DA-
Programmable address indication bit (wake-up
bit) and user invisible compare logic to support
multiple microcomputer networking. Optional
character search function.
Internal diagnostic capabilities:
Separate interrupt/DMA channels for transmit
and receive.
In addition, a Synchronous mode supports:
DCD
RECEIVER
REGISTER
RECEIVER
REGISTER
BUFFER
isolation.
tion.
DCD signals).
data SIN/SOUT.
for clocks CLKOUT/RXCL.
nals.
TA, CLOCKs and CONTROLs.
SHIFT
SIN
VA00169A