MPC564EVB Freescale Semiconductor, MPC564EVB Datasheet - Page 198

• Manufacturer Part Number: MPC564EVB
• Description: KIT EVAL FOR MPC561/562/563/564
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC564EVB

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC56x
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet
• For Use With/related Products: MPC561, 562, 563, 564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Central Processing Unit
When a decrementer exception is taken, instruction execution resumes at offset 0x0900 from the physical
base address indicated by MSR[IP].
3.15.4.10 System Call Exception (0x0C00)
A system call exception occurs when a system call instruction is executed. The effective address of the
instruction following the sc instruction is placed into SRR0. MSR[16:31] are placed into SRR1[16:31],
and SRR1[0:15] are set to undefined values. Then a system call exception is generated.
The system call instruction is context synchronizing. That is, when a system call exception occurs,
instruction dispatch is halted and the following synchronization is performed:
Register settings are shown in
When a system call exception is taken, instruction execution resumes at offset 0x00C00 from the physical
base address indicated by MSR[IP].
3.15.4.11 Trace Exception (0x0D00)
A trace interrupt occurs if MSR[SE] = 1 and any instruction except rfi is successfully completed or
MSR[BE]= 1 and a branch is completed. Notice that the trace interrupt does not occur after an instruction
that caused an interrupt (for instance, sc). Monitor/debugger software must change the vectors of other
3-54
1
1. The exception mechanism waits for all instructions in execution to complete to a point where they
2. The processor ensures that all instructions in execution complete in the context in which they began
3. Instructions dispatched after the exception is processed are fetched and executed in the context
1
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
Machine State Register (MSR)
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain a
compressed address.
If the exception occurs during a data access in Decompression On mode, the SRR0 register will contain the address
of the Load/Store instruction in compressed format. If the exception occurs during an instruction fetch in
decompression on mode, the SRR0 register will contain an indeterminate value.
report all exceptions they will cause.
execution.
established by the exception mechanism.
Register
Table 3-31. Register Settings following a System Call Exception
Table
1
MPC561/MPC563 Reference Manual, Rev. 1.2
DCMPEN
3-31.
[16:31]
[0:15]
Other
ME
LE
All
IP
Set to the effective address of the instruction following the
System Call instruction
Undefined
Loaded from MSR[16:31]
No change
No change
Set to value of ILE bit prior to the exception
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Cleared to 0
Setting Description
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