MPC564EVB Freescale Semiconductor, MPC564EVB Datasheet - Page 866
![KIT EVAL FOR MPC561/562/563/564](/photos/39/39/393946/mpc564evbimage_sml.jpg)
MPC564EVB
Manufacturer Part Number
MPC564EVB
Description
KIT EVAL FOR MPC561/562/563/564
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Specifications of MPC564EVB
Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MPC56x
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet
For Use With/related Products
MPC561, 562, 563, 564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 866 of 1420
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CDR3 Flash (UC3F) EEPROM
21.1
The UC3F module contains a memory interface (MI) and an array core. The MI controls access of the array
core and register block in the UC3F module.
The interface signals to the UC3F module consist of address inputs, data inputs, data outputs, a simple set
of control signals for read and write operations, a set of register selects, and a set of register outputs which
are used by the BIU. Three required supply pins power the module: V
The UC3F module is a fully asynchronous module and does not require a clock input for operation. All
required clocks are generated internally using an internal oscillator, external test clock input, or internal
delay circuits.
21.1.1
The UC3F EEPROM module uses external pins to provide power supplies. These pins are listed in
Table
21-4
.
Mnemoni
VFLASH
B0EPEE
EPEE
V
V
21-1.
DDF
SSF
c
UC3F Interface
External Interface
Program/Eras
Program/Eras
Ground Pin
Power Pin
Power Pin
I/O Type
External
External
Block 0
e
e
UC3F 5-V power supply VFLASH provides a 5-V supply to the UC3F module which is used
UC3F power supply
EPEE pin status
EPEE pin status
Table 21-1. UC3F External Interface Signals
UC3F ground
Description
MPC561/MPC563 Reference Manual, Rev. 1.2
Block 0
To reduce noise in the read path no other circuits should be
connected to the UC3F V
isolated from all other V
voltage range during operation is 2.6 V ± 0.1 V.
To reduce noise in the read path no other circuits should be
connected to the UC3F V
from all other V
for read, program, and erase operations. VFLASH must be in the
range of 4.75 V to 5.25 V (5 V ± 5%) during operation.
The EPEE bit monitors the state of the external program/erase
enable (EPEE) input. The UC3F module samples the EPEE input
when EHV is asserted and holds that sampled state until EHV is
negated.
The B0EM bit monitors the state of Block 0 EPEE, B0EPEE, input.
The UC3F module samples the B0EPEE input when EHV is
asserted and holds that sampled value until EHV is negated.
If B0EM = 1 when EHV is asserted, high voltage operations such
as program or erase are enabled for either small block 0 or the
lowest numbered block of the UC3F array regardless of the state
of EPEE.
If B0EM = 0 when EHV is asserted, high voltage operations are
disabled for small block 0 or the lowest numbered block of the
UC3F array regardless of the state of EPEE.
SS
pins inside the device.
DD
SSF
DDF
DDF
Comments
pins inside the device. The specified
supply. This V
supply pin.This V
, V
SSF
, and V
SS
Freescale Semiconductor
pin must be isolated
DD
FLASH
pin must be
.
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