MPC564EVB Freescale Semiconductor, MPC564EVB Datasheet - Page 635

• Manufacturer Part Number: MPC564EVB
• Description: KIT EVAL FOR MPC561/562/563/564
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC564EVB

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC56x
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet
• For Use With/related Products: MPC561, 562, 563, 564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

To ensure proper operation, set the QSPI enable bit (SPE) in SPCR1 only after initializing the other control
registers. Setting this bit starts the QSPI.
Rewriting the same value to a control register does not affect QSPI operation with the exception of writing
NEWQP in SPCR2. Rewriting the same value to these bits causes the RAM queue pointer to restart
execution at the designated location.
Before changing control bits, the QSPI should be halted. Writing a different value into a control register
other than SPCR2 while the QSPI is enabled may disrupt operation. SPCR2 is buffered, preventing any
disruption of the current serial transfer. After the current serial transfer is completed, the new SPCR2 value
becomes effective.
15.6.1.1
SPCR0 contains parameters for configuring the QSPI before it is enabled. The CPU has read/write access
to SPCR0, but the QSPI has read access only. SPCR0 must be initialized before QSPI operation begins.
Writing a new value to SPCR0 while the QSPI is enableddisrupts operation.
Freescale Semiconductor
1
2
SRESET
Access
S = Supervisor access only
S/U = Supervisor access only or unrestricted user access (assignable data space).
Eight-bit registers, such as SPCR3 and SPSR, are on 8-bit boundaries. 16-bit registers such as SPCR0 are on 16-bit
boundaries.
S/U
S/U
Field MSTR WOMQ
Addr
1
QSPI Control Register 0 (SPCR0)
MSB
0x30 51C0 –
0x30 5180 –
0
0
0x30 51BF
0x30 51DF
Address
0
1
MSB
0
2
Figure 15-11. QSPI Control Register 0 (SPCR0)
Table 15-12. QSPI Register Map (continued)
2
MPC561/MPC563 Reference Manual, Rev. 1.2
3
BITS
0000
4
5
CPOL CPHA
0
6
Transmit Data RAM (32 half-words)
0x30 5018
Command RAM (32 bytes)
1
7
8
9
10
Queued Serial Multi-Channel Module
0000_0100
11
SPBR
12
13
14
LSB
LSB
15
15
15-17