MPC564EVB Freescale Semiconductor, MPC564EVB Datasheet - Page 427

• Manufacturer Part Number: MPC564EVB
• Description: KIT EVAL FOR MPC561/562/563/564
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC564EVB

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC56x
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet
• For Use With/related Products: MPC561, 562, 563, 564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Because it takes two clocks for the external address to be recognized and handled by the memory
controller, the TS which is generated by the external master is ahead of the corresponding CS and strobes
which are asserted by the memory controller. This 2-clock delay might cause problems in some
synchronous memories. To overcome this, the memory controller generates the MTS (memory transfer
start) strobe which can be used in the slave’s memory instead of the external master’s TS signal. As seen
in
the external memory can latch the external master’s address correctly. To activate this feature, the MTSC
bit must be set in the SIUMCR register. Use external logic to control devices that can have burst accesses
from an external master.
On the MPC563, when the external master accesses the internal Flash when it is disabled, the access is
terminated with the transfer error acknowledge (TEA) signal asserted, and the memory controller does not
support this access in any way.
When the memory controller serves an external master, the BDIP signal becomes an input signal. This
signal is watched by the memory controller to detect when the burst is terminated.
Freescale Semiconductor
Figure
NOTE: The memory controller’s BDIP line is used as a burst_in_progress signal.
10-20, the MTS strobe is synchronized to the assertion of CS by the memory controller so that
MPC5xx
Address
BURST
WE/BE
MTS
BDIP
Data
TS
CSx
TA
OE
Configuration for GPCM-Handled Memory Devices
Figure 10-20. Synchronous External Master
TA
MPC561/MPC563 Reference Manual, Rev. 1.2
TS
Synchronous External Master
BDIP
Data
ADDR
BURST
BDIP
BURST
TS
CE
OE
W
Data
Address
Memory
Memory Controller
10-29