dm74as373 Fairchild Semiconductor, dm74as373 Datasheet

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dm74as373

Manufacturer Part Number
dm74as373
Description
Octal D-type Transparent Latch With 3-state Outputs
Manufacturer
Fairchild Semiconductor
Datasheet

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dm74as373N
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© 2000 Fairchild Semiconductor Corporation
DM74AS373WM
DM74AS373N
DM74AS373
Octal D-Type Transparent Latch with 3-STATE Outputs
General Description
These 8-bit registers feature totem-pole 3-STATE outputs
designed specifically for driving highly-capacitive or rela-
tively low-impedance loads. The high-impedance state and
increased high-logic-level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for inter-
face or pull-up components. They are particularly attractive
for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight latches of the DM74AS373 are transparent D-
type latches, meaning that while the enable (G) is HIGH
the Q outputs will follow the data (D) inputs. When the
enable is taken LOW the output will be latched at the level
of the data that was set up.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (HIGH or LOW
logic levels) or a high impedance state. In the high-imped-
ance state the outputs neither load nor drive the bus lines
significantly.
The output control does not affect the internal operation of
the latches. That is, the old data can be retained or new
data can be entered even while the outputs are OFF.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number
Package Number
M20B
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DS006309
Features
Switching specifications at 50 pF
Switching specifications guaranteed over full tempera-
ture and V
Advanced oxide-isolated, ion-implanted Schottky TTL
process
Functionally and pin for pin compatible with LS and ALS
TTL counterparts
Improved AC performance over LS and ALS TTL coun-
terparts
3-STATE buffer-type outputs drive bus lines directly
Package Description
CC
range
April 1984
Revised March 2000
www.fairchildsemi.com

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dm74as373 Summary of contents

Page 1

... They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the DM74AS373 are transparent D- type latches, meaning that while the enable (G) is HIGH the Q outputs will follow the data (D) inputs. When the enable is taken LOW the output will be latched at the level of the data that was set up ...

Page 2

Logic Diagram www.fairchildsemi.com Function Table Output Enable Control LOW State H HIGH State X Don’t Care Z High Impedance State Q Previous Condition of Q ...

Page 3

Absolute Maximum Ratings Supply Voltage Input Voltage Voltage Applied to Disabled Output Operating Free Air Temperature Range Storage Temperature Range Typical JA N Package M Package Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage ...

Page 4

Switching Characteristics over recommended operating free air temperature range Symbol Parameter t Propagation Delay Time PLH LOW-to-HIGH Level Output t Propagation Delay Time PHL HIGH-to-LOW Level Output t Propagation Delay Time PLH LOW-to-HIGH Level Output t Propagation Delay Time PHL ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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