dm74as74 Fairchild Semiconductor, dm74as74 Datasheet

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dm74as74

Manufacturer Part Number
dm74as74
Description
Dual D-type Positive-edge-triggered Flip-flop With Preset And Clear
Manufacturer
Fairchild Semiconductor
Datasheet

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© 2000 Fairchild Semiconductor Corporation
DM74AS74M
DM74AS74SJX
DM74AS74N
DM74AS74
Dual D-Type Positive-Edge-Triggered Flip-Flop
with Preset and Clear
General Description
The AS74 is a dual edge-triggered flip-flops. Each flip-flop
has individual D, clock, clear and preset inputs, and also
complementary Q and Q outputs.
Information at input D is transferred to the Q output on the
positive going edge of the clock pulse. Clock triggering
occurs at a voltage level of the clock pulse and is not
directly related to the transition time of the positive going
pulse. When the clock input is at either the HIGH or LOW
level, the D input signal has no effect.
Asynchronous preset and clear inputs will set or clear Q
output respectively upon the application of LOW level sig-
nal.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number
Package Number
M14D
M14A
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DS006282
Features
Function Table
L
H
X
Q
Note 1: This condition is nonstable; it will not persist when preset and clear
inputs return to their inactive (HIGH) level. The output levels in this condi-
tion are not guaranteed to meet the V
0
Switching specifications at 50 pF
Switching specifications guaranteed over full tempera-
ture and V
Advanced oxide-isolated, ion-implanted Schottky TTL
process
Functionally and pin-for-pin compatible with Schottky
and LS TTL counterpart
Improved AC performance over S74 at approximately
half the power
LOW State
Positive Edge Transition
Don't Care
HIGH State
Previous Condition of Q
PR
H
H
H
H
L
L
Package Description
CLR CLK
CC
H
H
H
H
L
L
Inputs
range
X
X
X
L
D
X
X
X
H
X
L
OH
April 1984
Revised March 2000
H (Note 1)
specification.
Q
Q
H
H
L
L
0
Outputs
www.fairchildsemi.com
H (Note 1)
Q
Q
H
H
L
L
0

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dm74as74 Summary of contents

Page 1

... Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74AS74SJX M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74AS74N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. ...

Page 2

Logic Diagram www.fairchildsemi.com 2 ...

Page 3

Absolute Maximum Ratings Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Typical JA N Package M Package Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input ...

Page 4

Switching Characteristics over recommended operating free air temperature range Symbol Parameter f Maximum Clock Frequency V MAX t Propagation Delay Time R PLH LOW-to-HIGH Level Output C t Propagation Delay Time PHL HIGH-to-LOW Level Output t Propagation Delay Time PLH ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M14A 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M14D 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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