PIC18F26K20-E/SO Microchip Technology, PIC18F26K20-E/SO Datasheet - Page 34

• Manufacturer Part Number: PIC18F26K20-E/SO
• Description: IC PIC MCU FLASH 16KX16 28-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26K20-E/SO

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: CCP/ECCP/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Package: 28SOIC W
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 64 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPAC164303 - MODULE SKT FOR PM3 64TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2XK20/4XK20
2.5.3
The Low-Frequency Internal Oscillator (LFINTOSC) is
a 31 kHz internal clock source.
The output of the LFINTOSC connects to internal
oscillator block frequency selection multiplexer (see
Figure 2-1). Select 31 kHz, via software, using the
IRCF<2:0> bits of the OSCCON register and the
INTSRC
Section 2.5.4 “Frequency Select Bits (IRCF)” for
more information. The LFINTOSC is also the frequency
for the Power-up Timer (PWRT), Watchdog Timer
(WDT) and Fail-Safe Clock Monitor (FSCM).
The LFINTOSC is enabled when any of the following
are enabled:
• IRCF<2:0> bits of the OSCCON register = 000 and
• Power-up Timer (PWRT)
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor (FSCM)
2.5.4
The output of the 16 MHz HFINTOSC and 31 kHz
LFINTOSC connects to a postscaler and multiplexer
(see Figure 2-1). The Internal Oscillator Frequency
Select bits IRCF<2:0> of the OSCCON register select
the output frequency of the internal oscillators. One of
eight frequencies can be selected via software:
• 16 MHz
• 8 MHz
• 4 MHz
• 2 MHz
• 1 MHz (Default after Reset)
• 500 kHz
• 250 kHz
• 31 kHz (LFINTOSC or HFINTOSC/512)
DS41303G-page 34
INTSRC bit of the OSCTUNE register = 0
Note:
bit
LFINTOSC
FREQUENCY SELECT BITS (IRCF)
Following any Reset, the IRCF<2:0> bits of
the OSCCON register are set to ‘011’ and
the frequency selection is set to 1 MHz.
The user can modify the IRCF bits to
select a different frequency.
of
the
OSCTUNE
register.
See
2.5.5
The factory calibrates the internal oscillator block output
(HFINTOSC) for 16 MHz. However, this frequency may
drift as V
controller operation in a variety of ways. It is possible to
adjust the HFINTOSC frequency by modifying the value
of the TUN<5:0> bits in the OSCTUNE register. This has
no effect on the LFINTOSC clock source frequency.
Tuning the HFINTOSC source requires knowing when to
make the adjustment, in which direction it should be
made and in some cases, how large a change is
needed. Three possible compensation techniques are
discussed in the following sections, however other tech-
niques may be used.
2.5.5.1
An adjustment may be required when the USART
begins to generate framing errors or receives data with
errors while in Asynchronous mode. Framing errors
indicate that the device clock frequency is too high; to
adjust for this, decrement the value in OSCTUNE to
reduce the clock frequency. On the other hand, errors
in data may suggest that the clock speed is too low; to
compensate, increment OSCTUNE to increase the
clock frequency.
2.5.5.2
This technique compares device clock speed to some
reference clock. Two timers may be used; one timer is
clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Timer1 oscillator.
Both timers are cleared, but the timer clocked by the
reference generates interrupts. When an interrupt
occurs, the internally clocked timer is read and both
timers are cleared. If the internally clocked timer value
is greater than expected, then the internal oscillator
block is running too fast. To adjust for this, decrement
the OSCTUNE register.
2.5.5.3
A CCP module can use free running Timer1 (or Timer3),
clocked by the internal oscillator block and an external
event with a known period (i.e., AC power frequency).
The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use later.
When the second event causes a capture, the time of the
first event is subtracted from the time of the second
event. Since the period of the external event is known,
the time difference between events can be calculated.
If the measured time is much greater than the calcu-
lated time, the internal oscillator block is running too
fast; to compensate, decrement the OSCTUNE register.
If the measured time is much less than the calculated
time, the internal oscillator block is running too slow; to
compensate, increment the OSCTUNE register.
DD
or temperature changes, which can affect the
HFINTOSC FREQUENCY DRIFT
Compensating with the USART
Compensating with the Timers
Compensating with the CCP Module
in Capture Mode
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