PIC18F26K20-E/SO Microchip Technology, PIC18F26K20-E/SO Datasheet - Page 44

• Manufacturer Part Number: PIC18F26K20-E/SO
• Description: IC PIC MCU FLASH 16KX16 28-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26K20-E/SO

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: CCP/ECCP/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Package: 28SOIC W
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 64 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPAC164303 - MODULE SKT FOR PM3 64TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2XK20/4XK20
3.1.3
The length of the transition between clock sources is
the sum of:
• Start-up time of the new clock
• Two and one half cycles of the old clock source
• Two and one half cycles of the new clock
Three flag bits indicate the current clock source and its
status. They are:
• OSTS (of the OSCCON register)
• IOFS (of the OSCCON register)
• T1RUN (of the T1CON register)
In general, only one of these bits will be set while in a
given power-managed mode. Table 3-2 shows the rela-
tionship of the flags to the active main system clock
source.
TABLE 3-2:
.
3.1.4
The power-managed mode that is invoked with the
SLEEP instruction is determined by the setting of the
IDLEN bit of the OSCCON register at the time the
instruction is executed. All clocks stop and minimum
power is consumed when SLEEP is executed with the
IDLEN bit cleared. The system clock continues to sup-
ply a clock to the peripherals but is disconnected from
the CPU when SLEEP is executed with the IDLEN bit
set.
DS41303G-page 44
OSTS IOFS T1RUN
1
0
0
1
0
Note 1: Executing a SLEEP instruction does not
0
1
0
1
0
CLOCK TRANSITIONS AND
STATUS INDICATORS
MULTIPLE FUNCTIONS OF THE
SLEEP COMMAND
necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep mode or
one of the Idle modes, depending on the
setting of the IDLEN bit.
0
0
1
0
0
SYSTEM CLOCK INDICATORS
Main System Clock Source
HFINTOSC as primary clock
HFINTOSC is not yet stable
Secondary Oscillator
Primary Oscillator
LFINTOSC or
HFINTOSC
3.2
In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock source.
3.2.1
The PRI_RUN mode is the normal, full power execution
mode of the microcontroller. This is also the default
mode upon a device Reset, unless Two-Speed Start-
up is enabled (see Section 2.10 “Two-Speed Clock
Start-up Mode” for details). In this mode, the OSTS bit
is set. The IOFS bit will be set if the HFINTOSC is the
primary clock source and the oscillator is stable (see
Section 2.2 “Oscillator Control”).
3.2.2
The SEC_RUN mode is the mode compatible to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the Timer1 oscillator. This gives users the
option of lower power consumption while still using a
high accuracy clock source.
SEC_RUN mode is entered by setting the SCS<1:0>
bits to ‘01’. When SEC_RUN mode is active all of the
following are true:
• The main clock source is switched to the Timer1
• Primary oscillator is shut down
• T1RUN bit of the T1CON register is set
• OSTS bit is cleared.
On transitions from SEC_RUN mode to PRI_RUN, the
peripherals and CPU continue to be clocked from the
Timer1 oscillator while the primary clock is started.
When the primary clock becomes ready, a clock switch
back to the primary clock occurs (see Figure 2-7).
When the clock switch is complete, the T1RUN bit is
cleared, the OSTS bit is set and the primary clock is
providing the main system clock. The Timer1 oscillator
continues to run as long as the T1OSCEN bit is set.
oscillator
Note:
Run Modes
PRI_RUN MODE
SEC_RUN MODE
The Timer1 oscillator should already be
running prior to entering SEC_RUN mode.
If the T1OSCEN bit is not set when the
SCS<1:0> bits are set to ‘01’, entry to
SEC_RUN mode will not occur until
T1OSCEN bit is set and Timer1 oscillator
is ready.
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