PIC18F1320-I/SO Microchip Technology, PIC18F1320-I/SO Datasheet - Page 137

• Manufacturer Part Number: PIC18F1320-I/SO
• Description: IC MCU FLASH 4KX16 A/D 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1320-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 18-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 7-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA12XP080 - ADAPTER DEVICE FOR MPLAB-ICEAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16.2
The BRG is a dedicated 8-bit or 16-bit generator, that
supports both the Asynchronous and Synchronous
modes of the EUSART. By default, the BRG operates
in 8-bit mode; setting the BRG16 bit (BAUDCTL<3>)
selects 16-bit mode.
The SPBRGH:SPBRG register pair controls the period
of a free running timer. In Asynchronous mode, bits
BRGH (TXSTA<2>) and BRG16 also control the baud
rate. In Synchronous mode, bit BRGH is ignored.
Table 16-1 shows the formula for computation of the
baud rate for different EUSART modes which only
apply in Master mode (internally generated clock).
Given the desired baud rate and F
integer value for the SPBRGH:SPBRG registers can be
calculated using the formulas in Table 16-1. From this,
the error in baud rate can be determined. An example
calculation is shown in Example 16-1. Typical baud
rates and error values for the various asynchronous
modes
advantageous to use the high baud rate (BRGH = 1),
or the 16-bit BRG to reduce the baud rate error, or
achieve a slow baud rate for a fast oscillator frequency.
Writing a new value to the SPBRGH:SPBRG registers
causes the BRG timer to be reset (or cleared). This
ensures the BRG does not wait for a timer overflow
before outputting the new baud rate.
TABLE 16-1:
EXAMPLE 16-1:
 2004 Microchip Technology Inc.
Legend: x = Don’t care, n = value of SPBRGH:SPBRG register pair
For a device with F
Desired Baud Rate =
Solving for SPBRGH:SPBRG:
Calculated Baud Rate =
Error
SYNC
0
0
0
0
1
1
EUSART Baud Rate Generator
(BRG)
are
Configuration Bits
shown
X
OSC
BAUD RATE FORMULAS
BRG16
=
=
=
=
=
=
0
0
1
1
0
1
of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:
F
((F
((16000000/9600)/64) – 1
[25.042] = 25
16000000/(64 (25 + 1))
9615
(Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
(9615 – 9600)/9600 = 0.16%
CALCULATING BAUD RATE ERROR
OSC
in
OSC
/(64 ([SPBRGH:SPBRG] + 1))
Table 16-2.
/Desired Baud Rate)/64) – 1
BRGH
0
1
0
1
x
x
OSC
, the nearest
It
may
BRG/EUSART Mode
be
16-bit/Asynchronous
16-bit/Asynchronous
8-bit/Asynchronous
8-bit/Asynchronous
16-bit/Synchronous
8-bit/Synchronous
16.2.1
The system clock is used to generate the desired baud
rate; however, when a power managed mode is
entered, the clock source may be operating at a differ-
ent frequency than in PRI_RUN mode. In Sleep mode,
no clocks are present and in PRI_IDLE mode, the
primary clock source continues to provide clocks to the
Baud Rate Generator; however, in other power
managed modes, the clock frequency will probably
change. This may require the value in SPBRG to be
adjusted.
If the system clock is changed during an active receive
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit
and make sure that the receive operation is Idle before
changing the system clock.
16.2.2
The data on the RB4/AN6/RX/DT/KBI0 pin is sampled
three times by a majority detect circuit to determine if a
high or a low level is present at the RX pin.
PIC18F1220/1320
POWER MANAGED MODE
OPERATION
SAMPLING
Baud Rate Formula
F
F
F
OSC
OSC
OSC
/[64 (n + 1)]
/[16 (n + 1)]
/[4 (n + 1)]
DS39605C-page 135