PIC18F1320-I/SO Microchip Technology, PIC18F1320-I/SO Datasheet - Page 187

• Manufacturer Part Number: PIC18F1320-I/SO
• Description: IC MCU FLASH 4KX16 A/D 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1320-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 18-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 7-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA12XP080 - ADAPTER DEVICE FOR MPLAB-ICEAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.5
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PICmicro devices.
The user program memory is divided into three blocks.
One of these is a boot block of 512 bytes. The remain-
der of the memory is divided into two blocks on binary
boundaries.
FIGURE 19-5:
TABLE 19-3:
 2004 Microchip Technology Inc.
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
Legend: Shaded cells are unimplemented.
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
File Name
Program Verification and
Code Protection
(Unimplemented
Memory Space)
Controlled By:
Block Code
Protection
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
SUMMARY OF CODE PROTECTION REGISTERS
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F1220/1320
WRTD
000000h
0001FFh
000200h
0007FFh
000800h
000FFFh
001000h
1FFFFFh
Bit 7
CPD
Address
Range
—
—
—
—
EBTRB
WRTB
Unimplemented
Bit 6
CPB
(PIC18F1220)
—
—
—
Boot Block
4 Kbytes
Read ‘0’s
MEMORY SIZE/DEVICE
Block 0
Block 1
WRTC
Bit 5
—
—
—
—
—
Unimplemented
(PIC18F1320)
Boot Block
8 Kbytes
Read ‘0’s
Block 0
Block 1
Each of the three blocks has three protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 19-5 shows the program memory organization
for 4 and 8-Kbyte devices and the specific code protec-
tion bit associated with each block. The actual locations
of the bits are summarized in Table 19-3.
Bit 4
—
—
—
—
—
—
PIC18F1220/1320
Bit 3
000000h
0001FFh
000200h
000FFFh
001000h
001FFFh
002000h
1FFFFFh
Address
—
—
—
—
—
—
Range
Bit 2
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
—
—
—
—
—
—
(Unimplemented
Memory Space)
Controlled By:
Block Code
Protection
EBTR1
WRT1
Bit 1
CP1
DS39605C-page 185
—
—
—
EBTR0
WRT0
Bit 0
CP0
—
—
—