PIC24FJ64GA006-I/PT Microchip Technology, PIC24FJ64GA006-I/PT Datasheet
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PIC24FJ64GA006-I/PT Summary of contents
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... PIC24FJ128GA010 Family © 2009 Microchip Technology Inc. 64/80/100-Pin General Purpose, 16-Bit Flash Microcontrollers Data Sheet DS39747E ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Oscillator Start-up Timer (OST) • Flexible Watchdog Timer (WDT) with On-Chip, Low-Power RC Oscillator for Reliable Operation • In-Circuit Serial Programming™ (ICSP™) and In-Circuit Emulation (ICE) via 2 Pins Program Device Pins Memory (Bytes) PIC24FJ64GA006 64 64K PIC24FJ96GA006 64 96K PIC24FJ128GA006 64 128K PIC24FJ64GA008 ...
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... PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGC1/EMUC1/V -/AN1/CN3/RB1 REF PGD1/EMUD1/PMA6/V +/AN0/CN2/RB0 REF DS39747E-page PIC24FJXXGA006 8 PIC24FJXXXGA006 SOSCO/T1CK/CN0/RC14 47 SOSCI/CN1/RC13 46 OC1/RD0 45 IC4/PMCS1/INT4/RD11 44 IC3/PMCS2/INT3/RD10 43 IC2/U1CTS/INT2/RD9 42 IC1/RTCC/INT1/RD8 41 Vss 40 OSC2/CLKO/RC15 39 OSC1/CLKI/RC12 SCL1/RG2 36 SDA1/RG3 35 U1RTS/BCLK1/SCK1/INT0/RF6 34 U1RX/SDI1/RF2 33 U1TX/SDO1/RF3 © 2009 Microchip Technology Inc. ...
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... T2CK/RC1 4 T4CK/RC3 5 PMA5/SCK2/CN8/RG6 6 PMA4/SDI2/CN9/RG7 7 PMA3/SDO2/CN10/RG8 8 MCLR 9 PMA2/SS2/CN11/RG9 TMS/INT1/RE8 13 TDO/INT2/RE9 14 C1IN+/AN5/CN7/RB5 15 C1IN-/AN4/CN6/RB4 16 C2IN+/AN3/CN5/RB3 17 C2IN-/AN2/SS1/CN4/RB2 18 PGC1/EMUC1/AN1/CN3/RB1 19 PGD1/EMUD1/AN0/CN2/RB0 20 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY PIC24FJXXGA008 51 50 PIC24FJXXXGA008 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/RD11 IC3/PMCS2/RD10 IC2/RD9 IC1/RTCC/RD8 SDA2/INT4/RA15 SCL2/INT3/RA14 V SS OSC2/CLKO/RC15 OSC1/CLKI/RC12 ...
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... C1IN+/AN5/CN7/RB5 20 C1IN-/AN4/CN6/RB4 21 C2IN+/AN3/CN5/RB3 22 C2IN-/AN2/SS1/CN4/RB2 23 PGC1/EMUC1/AN1/CN3/RB1 24 PGD1/EMUD1/AN0/CN2/RB0 25 DS39747E-page PIC24FJXXGA010 63 PIC24FJXXXGA010 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/RD11 IC3/PMCS2/RD10 IC2/RD9 IC1/RTCC/RD8 INT4/RA15 INT3/RA14 V SS OSC2/CLKO/RC15 OSC1/CLKI/RC12 V DD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 © 2009 Microchip Technology Inc. ...
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... Electrical Characteristics .......................................................................................................................................................... 211 27.0 Packaging Information.............................................................................................................................................................. 225 Appendix A: Revision History............................................................................................................................................................. 231 Index ................................................................................................................................................................................................. 233 The Microchip Web Site ..................................................................................................................................................................... 237 Customer Change Notification Service .............................................................................................................................................. 237 Customer Support .............................................................................................................................................................................. 237 Reader Response .............................................................................................................................................................................. 238 Product Identification System ............................................................................................................................................................ 239 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY DS39747E-page 7 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39747E-page 8 © 2009 Microchip Technology Inc. ...
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... DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC24FJ64GA006 • PIC24FJ64GA008 • PIC24FJ64GA010 • PIC24FJ96GA006 • PIC24FJ96GA008 • PIC24FJ96GA010 • PIC24FJ128GA006 • PIC24FJ128GA008 • PIC24FJ128GA010 This family introduces a new line of Microchip devices: a 16-bit microcontroller family with a broad peripheral feature set and enhanced computational performance ...
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... Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first. memory (64 Kbytes for devices, 96 Kbytes for pin features available on the © 2009 Microchip Technology Inc. ...
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... JTAG Boundary Scan 10-Bit Analog-to-Digital Module (input channels) Analog Comparators Resets (and Delays) POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode, Configuration Word Instruction Set Packages © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY DC – 32 MHz 96K 128K 64K 96K 32,768 44,032 ...
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... W Reg Array 17x17 Multiplier 16-Bit ALU (2) MCLR 10-Bit Timer4/5 RTCC ADC (1) CN1-22 SPI1/2 I2C1/2 (1) PORTA RA0:RA7, 16 RA9:RA10, RA14:15 (1) PORTB RB0:RB15 PORTC RC1:RC4, RC12:RC15 (1) PORTD 16 RD0:RD15 (1) PORTE RE0:RE9 (1) PORTF RF0:RF8, RF12:RF13 16 (1) PORTG RG0:RG9, RG12:RG15 Comparators PMP/PSP UART1/2 © 2009 Microchip Technology Inc. ...
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... CN13 52 66 CN14 53 67 CN15 54 68 CN16 55 69 CN17 31 39 Legend: TTL = TTL input buffer ANA = Analog level input/output © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY Input I/O Buffer 100-Pin 25 I ANA A/D Analog Inputs ANA 23 I ANA 22 I ANA 21 ...
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... In-Circuit Debugger and ICSP™ Programming Clock. 25 I/O ST In-Circuit Debugger and ICSP Programming Data. 26 I/O ST In-Circuit Debugger and ICSP™ Programming Clock. 27 I/O ST In-Circuit Debugger and ICSP Programming Data Schmitt Trigger input buffer 2 2 C™ C/SMBus input buffer I Description © 2009 Microchip Technology Inc. ...
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... PMD7 3 3 PMRD 53 67 PMWR 52 66 Legend: TTL = TTL input buffer ANA = Analog level input/output © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY Input I/O Buffer 100-Pin 44 I/O ST/TTL Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output (Master modes). 43 ...
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... PORTA Digital I/ I/O ST PORTB Digital I/ I/O ST PORTC Digital I/ Schmitt Trigger input buffer C™ C/SMBus input buffer Description © 2009 Microchip Technology Inc. ...
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... RF5 32 40 RF6 35 45 RF7 — 44 RF8 — 43 RF12 — — RF13 — — Legend: TTL = TTL input buffer ANA = Analog level input/output © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY Input I/O Buffer 100-Pin 72 I/O ST PORTD Digital I/ I/O ...
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... Timer4 External Clock Input Timer5 External Clock Input JTAG Test Clock/Programming Clock Input JTAG Test Data/Programming Data Input — JTAG Test Data Output JTAG Test Mode Select Input Schmitt Trigger input buffer C™ C/SMBus input buffer Description © 2009 Microchip Technology Inc. ...
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... DDCORE REF REF V 9, 25, 41 11, 31, 51 15, 36, 45, SS Legend: TTL = TTL input buffer ANA = Analog level input/output © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY Input I/O Buffer 100-Pin UART1 Clear to Send Input — UART1 Request to Send Output UART1 Receive DIG UART1 Transmit Output ...
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... PIC24FJ128GA010 FAMILY NOTES: DS39747E-page 20 © 2009 Microchip Technology Inc. ...
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... Register Indirect modes. Each group offers addressing modes. Instructions are associated with predefined addressing modes depending upon their functional requirements. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY For most instructions, the core is capable of executing a data (or program data) memory read, a working reg- ister (data) read, a data memory write and a program (instruction) memory read per instruction cycle ...
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... Decode & Control Control Signals to Various Blocks DS39747E-page 22 Data Bus Data Latch PCL Data RAM Address Loop Latch Control Logic 16 RAGU WAGU EA MUX ROM Latch 16 Instruction Reg Hardware Multiplier Register Array Divide Support 16-Bit ALU Peripheral Modules © 2009 Microchip Technology Inc. ...
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... W10 W11 W12 W13 W14 W15 22 Registers or bits shadowed for PUSH.S and POP.S instructions. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY Description Working Register Array 23-Bit Program Counter ALU STATUS Register Stack Pointer Limit Value Register Table Memory Page Address Register ...
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... The value in parentheses indicates the IPL when IPL3 = 1. DS39747E-page 24 U-0 U-0 — — (1) R-0 R/W-0 ( Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) U-0 U-0 R/W-0 — — DC bit 8 R/W-0 R/W-0 R/W bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... PSV: Program Space Visibility in Data Space Enable bit 1 = Program space visible in data space 0 = Program space not visible in data space bit 1-0 Unimplemented: Read as ‘0’ Note 1: User interrupts are disabled when IPL3 = 1. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY U-0 U-0 U-0 — — ...
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... All multi-bit shift instructions only support Register Direct Addressing for both the operand source and result destination. A full summary of instructions that use the shift operation is provided below in Table 2-2. Description © 2009 Microchip Technology Inc. ...
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... Registers Reserved DEVID (2) Note: Memory areas are not shown to scale. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY either the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping, as described in Section 3.3 “Interfacing Program and Data Memory Spaces”. ...
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... Instruction Width Word for devices in the FLASH CONFIGURATION WORDS FOR PIC24FJ128GA010 FAMILY DEVICES Program Configuration Memory Word (Words) Addresses 22,016 00ABFCh: 00ABFEh 32,768 00FFFCh: 00FFFEh 44,032 0157FCh: 0157FEh PC Address (lsw Address) 0 000000h 000002h 000004h 000006h © 2009 Microchip Technology Inc. ...
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... FFFFh Note: Data memory areas are not shown to scale. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY memory space (that is, when EA<15> used for implemented memory addresses, while the upper half (EA<15> reserved for the Program Space Visi- bility area (see Section 3.3.3 “Reading Data from Program Memory Using Program Space Visibility” ...
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... CRC — — System NVM/PMD — xxA0 xxC0 xxE0 Interrupts — — — — — I/O — — — — — — — — — — I/O — — — © 2009 Microchip Technology Inc. ...
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TABLE 3-3: CPU CORE REGISTERS MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 ...
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TABLE 3-4: INTERRUPT CONTROLLER REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 INTCON1 0080 NSTDIS — — — INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 U2TXIF U2RXIF INT2IF ...
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TABLE 3-5: ICN REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CNEN2 0062 — — — — CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE ...
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TABLE 3-7: INPUT CAPTURE REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — IC3BUF 0148 IC3CON 014A — — ICSIDL ...
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TABLE 3-9: I2C1 REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 I2C1RCV 0200 — — — — I2C1TRN 0202 — — — — I2C1BRG 0204 — — — — I2C1CON 0206 I2CEN — I2CSIDL SCLREL ...
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TABLE 3-11: UART1 REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 U1MODE 0220 UARTEN — USIDL IREN U1STA 0222 UTXISEL1 TXINV UTXISEL0 — U1TXREG 0224 — — — — U1RXREG 0226 — — — — ...
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TABLE 3-15: ADC REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ...
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TABLE 3-17: PORTB REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 (1) TRISB 02C6 TRISB15 TRISB14 TRISB13 TRISB12 (1) PORTB 02C8 RB15 RB14 RB13 RB12 (1) LATB 02CA LATB15 LATB14 LATB13 LATB12 (1) ODCB 06C6 ...
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TABLE 3-20: PORTE REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISE 02D8 — — — — PORTE 02DA — — — — LATE 02DC — — — — ODCE 06D8 — — — — ...
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TABLE 3-24: PARALLEL MASTER/SLAVE PORT REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 PMCON 0600 PMPEN — PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN PMMODE 0602 BUSY IRQM1 IRQM0 INCM1 (1) PMADDR CS2 CS1 0604 (1) ...
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TABLE 3-27: CRC REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 CRCCON 0640 — — CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT CRCXOR 0642 CRCDAT 0644 CRCWDAT 0646 Legend: — = unimplemented, read as ...
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... Table 3-31 and Figure 3-5 show how the program EA is created for table operations and remapping accesses from the data EA. Here, P<23:0> refers to a program space word, whereas D<15:0> refers to a data space word. © 2009 Microchip Technology Inc. ...
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... Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY Program Space Address <23> ...
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... TBLRDL.B (Wn<0> TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. 800000h Only read operations are shown; write operations are also valid in the user memory area. Data EA<15:0> © 2009 Microchip Technology Inc. ...
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... PSVPAG is mapped into the upper half of the data memory space.... © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 24-bit program word are used to contain the data. The upper 8 bits of any program space locations used as data should be programmed with ‘1111 ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed ...
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... PIC24FJ128GA010 FAMILY NOTES: DS39747E-page 46 © 2009 Microchip Technology Inc. ...
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... Counter Using Table Instruction User/Configuration Space Select © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user ...
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... Configuration Word values are stored in the last two locations of program memory. Performing a page erase operation on the last page of program memory clears these values and enables code protection result, avoid performing page erase operations on the last page of program memory. required for © 2009 Microchip Technology Inc. ...
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... Memory row program operation (ERASE = operation (ERASE = 1) Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP3:NVMOP0 are unimplemented. 3: Available in ICSP™ mode only. Refer to device programming specification. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY (1) U-0 U-0 — — ...
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... Initialize in-page EA[15:0] pointer ; Set base address of erase block ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted © 2009 Microchip Technology Inc. ...
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... W0 MOV W0, NVMKEY MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR BTSC NVMCON, #15 BRA $-2 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY ; ; Initialize NVMCON ; ; Initialize PM Page Boundary SFR ; An example program memory address ; ; ; Write PM low word into program latch ; Write PM high byte into program latch ; ; ...
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... Write PM low word into program latch ; Write PM high byte into program latch ; ; Set NVMOP bits to 0011 ; Disable interrupts while the KEY sequence is written ; Write the key sequence ; Start the write cycle © 2009 Microchip Technology Inc. ...
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... Reset Enable Voltage Regulator Trap Conflict Illegal Opcode Uninitialized W Register Configuration Word Mismatch Reset © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY Note: Refer to the specific peripheral or CPU section of this manual for register Reset states. All types of device Reset will set a corresponding status bit in the RCON register to indicate the type of Reset (see Register 5-1) ...
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... SWDTEN bit setting. DS39747E-page 54 (1) U-0 U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) R/W-0 R/W-0 — CM VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... SWITCHING ENABLED) Reset Type Clock Source Determinant POR Oscillator Configuration bits (FNOSC2:FNOSC0) BOR MCLR COSC Control bits (OSCCON<14:12>) WDTR SWR © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY Setting Event POR POR POR POR PWRSAV instruction, POR POR POR — — 5.2 ...
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... RST OST LOCK T — RST T — RST T — RST T — RST T — RST T — RST PWRT FSCM Notes Delay — FSCM FSCM FSCM — FSCM FSCM FSCM — 3 — 3 — 3 — 3 — 3 — 3 (64 ms nominal) if on-chip © 2009 Microchip Technology Inc. ...
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... PLL to stabilize. In most cases, the FSCM delay will prevent an oscillator failure trap at a device Reset when the PWRT is disabled. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 5.3 Special Function Register Reset ...
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... PIC24FJ128GA010 FAMILY NOTES: DS39747E-page 58 © 2009 Microchip Technology Inc. ...
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... PIC24FJ128GA010 family devices implement non- maskable traps and unique interrupts. These are summarized in Table 6-1 and Table 6-2. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 6.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT as shown in Figure 6-1 ...
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... Alternate Interrupt Vector Table (AIVT) 00017Ch 00017Eh 000180h 0001FEh 000200h AIVT Address 000104h Reserved 000106h Oscillator Failure 000108h Address Error 00010Ah Stack Error 00010Ch Math Error 00010Eh Reserved 000110h Reserved 0001172h Reserved (1) (1) Trap Source © 2009 Microchip Technology Inc. ...
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... SPI1 Event SPI2 Error SPI2 Event Timer1 Timer2 Timer3 Timer4 Timer5 UART1 Error UART1 Receiver UART1 Transmitter UART2 Error UART2 Receiver UART2 Transmitter © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY Vector AIVT IVT Address Number Address 13 00002Eh 00012Eh 18 000038h 000138h 67 00009Ah ...
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... The CORCON register contains the IPL3 bit, which together with IPL2:IPL0, also indicates the current CPU priority level. IPL3 is a read-only bit so that trap events cannot be masked by the user software. All Interrupt registers are described in Register 6-1 through Register 6-30, in the following pages. © 2009 Microchip Technology Inc. ...
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... Note 1: See Register 2-2 for the description of remaining bit(s) that are not dedicated to interrupt control functions. 2: The IPL3 bit is concatenated with the IPL2:IPL0 bits (SR<7:5>) to form the CPU interrupt priority level. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY U-0 U-0 — ...
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... Unimplemented: Read as ‘0’ DS39747E-page 64 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 MATHERR ADDRERR STKERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 U-0 OSCFAIL — bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY U-0 U-0 U-0 — — ...
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... Interrupt request has not occurred DS39747E-page 66 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF U-0 R/W-0 R/W-0 — T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 SPF1IF T3IF bit 8 R/W-0 R/W-0 IC1IF INT0IF bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... MI2C1IF: Master I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY R/W-0 R/W-0 R/W-0 T5IF T4IF ...
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... Interrupt request has not occurred DS39747E-page 68 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2009 Microchip Technology Inc. R/W-0 U-0 OC5IF — bit 8 R/W-0 R/W-0 SPI2IF SPF2IF bit Bit is unknown ...
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... Interrupt request has not occurred bit 1 SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY U-0 U-0 U-0 — — — ...
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... Unimplemented: Read as ‘0’ DS39747E-page 70 U-0 U-0 U-0 — — — U-0 R/W-0 R/W-0 — CRCIF U2ERIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2009 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 U-0 U1ERIF — bit Bit is unknown ...
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... IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE ...
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... Interrupt request not enabled DS39747E-page 72 R/W-0 R/W-0 R/W-0 T5IE T4IE OC4IE R/W-0 R/W-0 R/W-0 INT1IE CNIE CMIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 U-0 OC3IE — bit 8 R/W-0 R/W-0 MI2C1IE SI2C1IE bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPF2IE: SPI2 Fault Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY U-0 U-0 U-0 — — — ...
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... Unimplemented: Read as ‘0’ DS39747E-page 74 U-0 U-0 U-0 — — — U-0 U-0 R/W-0 — — MI2C2IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2009 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 U-0 SI2C2IE — bit Bit is unknown ...
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... U2ERIE: UART2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY U-0 U-0 U-0 — — — U-0 ...
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... Interrupt source is disabled DS39747E-page 76 R/W-0 U-0 R/W-1 T1IP0 — OC1IP2 R/W-0 U-0 R/W-1 IC1IP0 — INT0IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC1IP1 OC1IP0 bit 8 R/W-0 R/W-0 INT0IP1 INT0IP0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... IC2IP2:IC2IP0: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY R/W-0 U-0 R/W-1 T2IP0 — OC2IP2 R/W-0 ...
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... Interrupt source is disabled DS39747E-page 78 R/W-0 U-0 R/W-1 U1RXIP0 — SPI1IP2 R/W-0 U-0 R/W-1 SPF1IP0 — T3IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 SPI1IP1 SPI1IP0 bit 8 R/W-0 R/W-0 T3IP1 T3IP0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP2:U1TXIP0: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY U-0 U-0 U-0 — — — R/W-0 ...
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... Interrupt source is disabled DS39747E-page 80 R/W-0 U-0 R/W-1 CNIP0 — CMIP2 R/W-0 U-0 R/W-1 MI2C1IP0 — SI2C1IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 CMIP1 CMIP0 bit 8 R/W-0 R/W-0 SI2C1IP1 SI2C1IP0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 2-0 INT1IP2:INT1IP0: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY U-0 U-0 U-0 — — — U-0 ...
Page 82
... Unimplemented: Read as ‘0’ DS39747E-page 82 R/W-0 U-0 R/W-1 T4IP0 — OC4IP2 R/W-0 U-0 U-0 OC3IP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC4IP1 OC4IP0 bit 8 U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 83
... Unimplemented: Read as ‘0’ bit 2-0 T5IP2:T5IP0: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY R/W-0 U-0 R/W-1 U2TXIP0 — U2RXIP2 R/W-0 ...
Page 84
... Interrupt source is disabled DS39747E-page 84 U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 SPI2IP0 — SPF2IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 SPF2IP1 SPF2IP0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 85
... IC3IP2:IC3IP0: Input Capture Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY R/W-0 U-0 R/W-1 IC5IP0 — IC4IP2 R/W-0 ...
Page 86
... PMPIP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 87
... SI2C2IP2:SI2C2IP0: Slave I2C2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY U-0 U-0 R/W-1 — — MI2C2IP2 R/W-0 ...
Page 88
... Unimplemented: Read as ‘0’ DS39747E-page 88 U-0 U-0 R/W-1 — — INT4IP2 R/W-0 U-0 U-0 INT3IP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 IN4IP1 INT4IP0 bit 8 U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 89
... RTCIP2:RTCIP0: Real-Time Clock/Calendar Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY U-0 U-0 R/W-1 — — RTCIP2 U-0 ...
Page 90
... Unimplemented: Read as ‘0’ DS39747E-page 90 R/W-0 U-0 R/W-1 CRCIP0 — U2ERIP2 R/W-0 U-0 U-0 U1ERIP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 U2ERIP1 U2ERIP0 bit 8 U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 91
... ISR will be re-entered immediately after exiting the rou- tine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 6.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, ...
Page 92
... PIC24FJ128GA010 FAMILY NOTES: DS39747E-page 92 © 2009 Microchip Technology Inc. ...
Page 93
... Secondary Oscillator SOSCO SOSCEN Enable SOSCI Oscillator © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY • On-chip 4x PLL to boost internal operating frequency on select internal and external oscillator sources • Software-controllable switching between various clock sources • Software-controllable postscaler for selective clocking of CPU for system power savings • ...
Page 94
... POSCMD1: Oscillator Source POSCMD0 Internal 11 Internal xx Internal 11 Secondary 11 Primary 10 Primary 01 Primary 00 Primary 10 Primary 01 Primary 00 Internal 11 Internal 11 bits, POSCMD1:POSCMD0 bits, FNOSC2:FNOSC0 FNOSC2: Note FNOSC0 1, 2 111 1 110 1 101 1 100 011 011 011 010 010 010 1 001 1 000 © 2009 Microchip Technology Inc. ...
Page 95
... Reset values for these bits are determined by the FNOSC Configuration bits. 2: Also resets to ‘0’ during any valid clock switch, or whenever a non-PLL Clock mode is selected. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY The Clock Divider register (Register 7-2) controls the features associated with Doze mode, as well as the postscaler for the FRC oscillator ...
Page 96
... Initiate an oscillator switch to clock source specified by NOSC2:NOSC0 bits 0 = Oscillator switch is complete Note 1: Reset values for these bits are determined by the FNOSC Configuration bits. 2: Also resets to ‘0’ during any valid clock switch, or whenever a non-PLL Clock mode is selected. DS39747E-page 96 © 2009 Microchip Technology Inc. ...
Page 97
... MHz (divide by 4) 001 = 4 MHz (divide by 2) 000 = 8 MHz (divide by 1) bit 7-0 Unimplemented: Read as ‘0’ Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY R/W-0 R/W-0 R/W-0 (1) DOZE0 ...
Page 98
... Minimum frequency deviation DS39747E-page 98 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 TUN4 TUN3 TUN2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 TUN1 TUN0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 99
... Perform the unlock sequence to allow a write to the OSCCON register low byte. 5. Set the OSWEN bit to initiate the oscillator switch. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY Once the basic sequence is completed, the system clock hardware responds automatically as follows: 1. The clock switching hardware compares the COSC status bits with the new value of the NOSC control bits ...
Page 100
... MOV.b ;OSCCONL (low byte) unlock sequence MOV MOV 57h to MOV MOV.b MOV.b ;Start oscillator switch operation BSET OSCCON, #0 BASIC CODE SEQUENCE FOR CLOCK SWITCHING #OSCCONH, w1 #0x78, w2 #0x9A, w3 w2, [w1] w3, [w1] WREG, OSCCONH #OSCCONL, w1 #0x46, w2 #0x57, w3 w2, [w1] w3, [w1] © 2009 Microchip Technology Inc. ...
Page 101
... PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY Note: SLEEP_MODE and IDLE_MODE are con- stants defined in the assembler include file for the selected device. 8.2.1 ...
Page 102
... By default, all modules that can operate during Idle mode will do so. Using the disable on Idle feature allows fur- ther reduction of power consumption during Idle mode, possible enhancing power savings for extremely critical power applications. © 2009 Microchip Technology Inc. ...
Page 103
... CK WR PORT Data Latch Read LAT Read PORT © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled ...
Page 104
... Make sure that DDCORE there is no external pull-up source when the internal pull-ups are enabled, as the voltage difference can cause a current path. Note: Pull-ups on change notification pins should always be disabled whenever the port pin is configured as a digital output. © 2009 Microchip Technology Inc. ...
Page 105
... SOSCO/ T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY Figure 10-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. Set the TON bit (= 1). 2. Select the timer prescaler ratio using the TCKPS1:TCKPS0 bits. ...
Page 106
... Unimplemented: Read as ‘0’ DS39747E-page 106 U-0 U-0 U-0 — — R/W-0 U-0 R/W-0 TCKPS0 — TSYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /2) U-0 U-0 — — — bit 8 R/W-0 U-0 TCS — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 107
... Timer2 and Timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 or Timer5 interrupt flags. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. Set the T32 bit (T2CON<3> or T4CON<3> ...
Page 108
... T2CON and T4CON registers. * The ADC Event Trigger is available only on Timer4/5. DS39747E-page 108 1x Gate Sync PR3 PR2 (PR5) (PR4) Comparator LSB TMR3 TMR2 (TMR4) (TMR5 TMR3HLD 16 (TMR5HLD) TCKPS1:TCKPS0 TON 2 Prescaler 1, 8, 64, 256 TGATE TCS Sync © 2009 Microchip Technology Inc. ...
Page 109
... Reset Equal FIGURE 11-3: TIMER3 AND TIMER5 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM T3CK (T5CK) TGATE 1 Set T3IF (T5IF) 0 Reset ADC Event Trigger* Equal * The ADC Event Trigger is available only on Timer4/5. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 1x Gate Sync TMR2 (TMR4) Sync ...
Page 110
... DS39747E-page 110 U-0 U-0 U-0 — — R/W-0 R/W-0 U-0 (1) TCKPS0 T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) /2) U-0 U-0 — — — bit 8 R/W-0 U-0 — TCS — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 111
... External clock from pin TyCK (on the rising edge Internal clock (F OSC bit 0 Unimplemented: Read as ‘0’ Note 1: When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timery operation; all timer functions are set through T2CON. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY U-0 U-0 (1) — — R/W-0 ...
Page 112
... PIC24FJ128GA010 FAMILY NOTES: DS39747E-page 112 © 2009 Microchip Technology Inc. ...
Page 113
... ICOV, ICBNE (ICxCON<4:3>) ICxCON System Bus Note: An ‘x’ signal, register or bit name denotes the number of the capture channel. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY • Capture timer value on every fourth rising edge of input applied at the ICx pin • Capture timer value on every 16th rising edge of input applied at the ICx pin • ...
Page 114
... Timer selections may vary. Refer to the device data sheet for details. DS39747E-page 114 U-0 U-0 U-0 — — — R-0, HC R/W-0, HC R/W-0 ICOV ICBNE ICM2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) U-0 U-0 — — bit 8 R/W-0 R/W-0 ICM1 ICM0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 115
... Single Compare Match mode • Dual Compare Match mode generating: - Single Output Pulse mode - Continuous Output Pulse mode • Simple Pulse-Width Modulation mode: - with Fault protection input - without Fault protection input © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY Set Flag bit (1) OCxIF Output S ...
Page 116
... When the compare time base and the value in its respective Period register match, the TMRy register resets to 0x0000 and resumes counting. 12. Steps 8 through 11 are repeated and a continuous stream of pulses is generated, indefinitely. The OCxIF flag is set on each OCxRS-TMRy compare match event. © 2009 Microchip Technology Inc. ...
Page 117
... Timer Period register. The PWM period can be calculated using Equation 13-1. EQUATION 13-2: CALCULATION FOR MAXIMUM PWM RESOLUTION Maximum PWM Resolution (bits) = Note 1: Based on F © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY EQUATION 13-1: PWM Period = [(PRy • T where: PWM Frequency = 1/[PWM Period] Note 1: Based on T PLL are disabled ...
Page 118
... FFFFh 7FFFh 0FFFh 244 Hz 488 Hz 3.9 kHz FFFFh 7FFFh 0FFFh ( MHz with PLL (32 MHz device OSC ( MHz) CY 3.9 kHz 31.3 kHz 125 kHz 03FFh 007Fh 001Fh ( MHZ) CY 15.6 kHz 125 kHz 500 kHz 03FFh 007Fh 001Fh © 2009 Microchip Technology Inc. ...
Page 119
... Output compare channel is disabled Note 1: Refer to the device data sheet for specific time bases available to the output compare module. 2: OCFA pin controls OC1-OC4 channels. OCFB pin controls the OC5 channel. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY U-0 U-0 U-0 — ...
Page 120
... PIC24FJ128GA010 FAMILY NOTES: DS39747E-page 120 © 2009 Microchip Technology Inc. ...
Page 121
... SPIx or separately as SPI1 and SPI2. Special Function Reg- isters will follow a similar notation. For example, SPIxCON refers to the control register for the SPI1 or SPI2 module. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY To set up the SPI module for the Standard Master mode of operation: 1. ...
Page 122
... SPIBEN bit (SPIxCON2<0>). 8. Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>). 1:1 to 1:8 Secondary Prescaler Select Edge Shift Control Transfer Write SPIxBUF 16 Internal Data Bus registers with MSTEN 1:1/4/16/64 F Primary CY Prescaler SPIxCON1<1:0> SPIxCON1<4:2> Enable Master Clock © 2009 Microchip Technology Inc. ...
Page 123
... Sync Control Control Clock SDOx bit0 SDIx SPIxSR Transfer 8-Level FIFO Receive Buffer SPIxBUF Read SPIxBUF © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 1:1 to 1:8 Secondary Prescaler Select Edge Shift Control Transfer 8-Level FIFO Transmit Buffer Write SPIxBUF 16 Internal Data Bus ...
Page 124
... DS39747E-page 124 U-0 U-0 R-0 — — SPIBEC2 R/W-0 R/W-0 R/W-0 SISEL2 SISEL1 SISEL0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R-0 R-0 SPIBEC1 SPIBEC0 bit 8 R-0 R-0 SPITBF SPIREF bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 125
... SPIxBUF location, reading SPIxRXB. In Enhanced Buffer mode: Automatically set in hardware when SPIx transfers data from SPIxSR to buffer, filling the last unread buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY DS39747E-page 125 ...
Page 126
... DS39747E-page 126 R/W-0 R/W-0 R/W-0 DISSCK DISSDO MODE16 R/W-0 R/W-0 R/W-0 SPRE2 SPRE1 SPRE0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 (1) SMP CKE bit 8 R/W-0 R/W-0 PPRE1 PPRE0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 127
... Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 SPIBEN: Enhanced Buffer Enable bit 1 = Enhanced Buffer enabled 0 = Enhanced Buffer disabled (Legacy mode) © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY U-0 U-0 U-0 — — ...
Page 128
... SDIx SDOx Serial Clock SCKx SCKx SSx SSx SSEN (SPIxCON1<7> and MSTEN (SPIxCON1<5> and (SPIxRXB) Shift Register (SPIxSR) LSb (SPIxTXB) SPIx Buffer (SPIxBUF) Shift Register (SPIxSR) MSb LSb 8-Level FIFO Buffer SPIx Buffer (SPIxBUF) SPIBEN (SPIxCON2<0> © 2009 Microchip Technology Inc. ...
Page 129
... FIGURE 14-7: SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM PIC24F (SPI Slave, Frame Slave) FIGURE 14-8: SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM PIC24F (SPI Master, Frame Slave) © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY PROCESSOR 2 SDOx SDIx SDIx SDOx Serial Clock SCKx ...
Page 130
... Microchip Technology Inc. ...
Page 131
... Bus Repeater mode, allowing the acceptance of all messages as a slave regardless of the address • Automatic SCL A block diagram of the module is shown in Figure 15-1. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 15.1 Communicating as a Master in a Single Master Environment The details of sending a message in Master mode depends on the communications protocol for the device being communicated with ...
Page 132
... Bit Detect Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSB Reload Control Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read © 2009 Microchip Technology Inc. ...
Page 133
... The above address bits will not cause an address match, independent of address mask settings. 2: Address will be Acknowledged only if GCEN = 1. 3: Match on this address can only occur on the upper byte in 10-Bit Addressing mode. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 15.3 Slave Address Masking The I2CxMSK register (Register 15-3) designates address bit positions as “ ...
Page 134
... R/W-0, HC R/W-0, HC R/W-0, HC ACKEN RCEN PEN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2 C pins are controlled by port functions slave slave slave) R/W-0 R/W-0 DISSLW SMEN bit 8 R/W-0, HC R/W-0, HC RSEN SEN bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 135
... SEN: Start Condition Enabled bit (when operating Initiate Start condition on SDA and SCL pins. Hardware clear at end of master Start sequence Start condition not in progress © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 2 C master. Applicable during master receive.) C master. Applicable during master receive.) ...
Page 136
... HSC = Hardware Settable/Clearable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2 C master. Applicable to master transmit operation module is busy 2 C slave) R-0, HSC R-0, HSC GCSTAT ADD10 bit 8 R-0, HSC R-0, HSC RBF TBF bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 137
... Hardware set when I2CxRCV written with received byte. Hardware clear when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 2 C slave device address byte. ...
Page 138
... Disable masking for bit x; bit match required in this position DS39747E-page 138 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 AMSK4 AMSK3 AMSK2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 AMSK9 AMSK8 bit 8 R/W-0 R/W-0 AMSK1 AMSK0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 139
... FIGURE 16-1: UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator Hardware Flow Control UARTx Receiver UARTx Transmitter © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY • Fully Integrated Baud Rate Generator with 16-Bit Prescaler • Baud Rates Ranging from 1 Mbps to 15 bps at 16 MIPS • ...
Page 140
... BRG timer to be reset (cleared). This ensures the BRG does not wait for a timer overflow before generating the new baud rate. /(16 * 65536). UART BAUD RATE WITH (1) BRGH = • (BRGx + – • Baud Rate = F /2; Doze mode CY OSC /4 CY (1) © 2009 Microchip Technology Inc. ...
Page 141
... Write ‘55h’ to UxTXREG – loads Sync character into the transmit FIFO. 5. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 16.5 Receiving in 8-Bit or 9-Bit Data Mode 1. ...
Page 142
... This feature is only available for the 16x BRG mode (BRGH = 0). DS39747E-page 142 R/W-0 R/W-0 U-0 (1) IREN RTSMD — R/W-0 R/W-0 R/W-0 RXINV BRGH PDSEL1 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 UEN1 UEN0 bit 8 R/W-0 R/W-0 PDSEL0 STSEL bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 143
... STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1: This feature is only available for the 16x BRG mode (BRGH = 0). © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY DS39747E-page 143 ...
Page 144
... U-0 R/W-0, HC R/W-0 — UTXBRK UTXEN R-1 R-0 R-0 RIDLE PERR FERR HC = Hardware Clearable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R-0 R-1 UTXBF TRMT bit 8 R/C-0 R-0 OERR URXDA bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 145
... Receive buffer has not overflowed (clearing a previously set OERR bit (1 → 0 transition) will reset the receiver buffer and the RSR to the empty state) bit 0 URXDA: Receive Buffer Data Available bit (read-only Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY DS39747E-page 145 ...
Page 146
... PIC24FJ128GA010 FAMILY NOTES: DS39747E-page 146 © 2009 Microchip Technology Inc. ...
Page 147
... PMP is highly configurable. FIGURE 17-1: PMP MODULE OVERVIEW PIC24F Parallel Master Port © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY Key features of the PMP module include: • Programmable Address Lines • Two Chip Select Lines • Programmable Strobe Options - Individual Read and Write Strobes or ...
Page 148
... DS39747E-page 148 R/W-0 R/W-0 R/W-0 ADRMUX1 ADRMUX0 PTBEEN (1) (1) R/W-0 R/W-0 R/W-0 CS2P CS1P BEP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (1) R/W-0 R/W-0 PTWREN PTRDEN bit 8 R/W-0 R/W-0 WRSP RDSP bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 149
... Read strobe active-high (PMRD Read strobe active-low (PMRD) For Master mode 1 (PMMODE<9:8> Read/write strobe active-high (PMRD/PMWR Read/write strobe active-low (PMRD/PMWR) Note 1: These bits have no effect when their corresponding pins are used as address lines. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY DS39747E-page 149 ...
Page 150
... DS39747E-page 150 R/W-0 R/W-0 R/W-0 INCM1 INCM0 MODE16 R/W-0 R/W-0 R/W-0 WAITM2 WAITM1 WAITM0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 MODE1 MODE0 bit 8 R/W-0 R/W-0 (1) (1) WAITE1 WAITE0 bit Bit is unknown (1) (1) © 2009 Microchip Technology Inc. ...
Page 151
... PMA<13:2> function as PMP address lines 0 = PMA<13:2> function as port I/O bit 1-0 PTEN1:PTEN0: PMALH/PMALL Strobe Enable bits 1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL 0 = PMA1 and PMA0 pads functions as port I/O © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY (1) R/W-0 R/W-0 R/W-0 ADDR< ...
Page 152
... Output buffer contains data that has not been transmitted DS39747E-page 152 U-0 R-0 R-0 — IB3F IB2F U-0 R-1 R-1 — OB3E OB2E U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R-0 R-0 IB1F IB0F bit 8 R-1 R-1 OB1E OB0E bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 153
... PMP module uses TTL input buffers 0 = PMP module uses Schmitt input buffers Note 1: To enable the actual RTCC output, the RTCCFG (RTCOE) bit needs to be set. 2: Refer to Table 1-2 for affected PMP inputs. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY U-0 U-0 U-0 — ...
Page 154
... PMDOUT2H (3) PMWR PMDOUT1<7:0> (0) PMDOUT2<7:0> (2) PMA<13:0> PMD<7:0> PMCS1 PMCS2 PMRD PMWR Address Bus Data Bus Control Lines Read Address Decode PMDIN1L (0) PMDIN1H (1) PMDIN2L (2) PMDIN2H (3) Input Register (Buffer) PMDIN1<7:0> (0) PMDIN1<15:8> (1) PMDIN2<7:0> (2) PMDIN2<15:8> (3) Address Bus Data Bus Control Lines © 2009 Microchip Technology Inc. ...
Page 155
... PMD<7:0> PMALL PMALH PMCS1 PMRD PMWR FIGURE 17-8: EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION PIC24F PMD<7:0> PMALL PMA<14:7> PMCS1 PMRD PMWR © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY PMA<13:8> PMD<7:0> PMA<7:0> PMCS1 PMCS2 PMALL PMRD PMWR PMD<7:0> PMA<13:8> PMCS1 PMCS2 PMALL ...
Page 156
... Parallel EEPROM A<n:0> D<7:0> Parallel EEPROM A<n:1> D<7:0> LCD Controller D<7:0> RS R/W E Address Bus Data Bus Control Lines Address Bus Data Bus Control Lines Address Bus Data Bus Control Lines Address Bus Data Bus Control Lines © 2009 Microchip Technology Inc. ...
Page 157
... RTCC Timer Alarm Event Comparator Compare Registers with Masks Repeat Counter © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY • 24-Hour Format (Military Time) • Calendar: Weekday, Date, Month and Year • Alarm Configurable • Year Range: 2000 to 2099 • Leap Year Correction • ...
Page 158
... RTCWREN bit (RCFGCAL<13>) must be YEAR set (refer to Example 18-1). bits //set the RTCWREN bit will be accessible through ALRMVAL REGISTER MAPPING Alarm Value Register Window ALRMVAL<15:8> ALRMVAL<7:0> ALRMMIN ALRMSEC ALRMWD ALRMHR ALRMMNTH ALRMDAY — — © 2009 Microchip Technology Inc. ...
Page 159
... Note 1: The RCFGCAL Reset value is dependent on type of Reset write to the RTCEN bit is only allowed when RTCWREN = 1. 3: This bit is read-only cleared to ‘0’ write to the lower half of the MINSEC register. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY R-0 R-0 R/W-0 (3) RTCSYNC ...
Page 160
... DS39747E-page 160 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) (1) U-0 U-0 — — bit 8 R/W-0 R/W-0 (1) (2) RTSECSEL PMPTTL bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... ARPT7:ARPT0: Alarm Repeat Counter Value bits 11111111 = Alarm will repeat 255 more times ... 00000000 = Alarm will not repeat The counter decrements on any alarm event. The counter is prevented from rolling over from 00h to FFh unless CHIME = 1. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY R/W-0 R/W-0 R/W-0 AMASK2 ...
Page 162
... DAYTEN0 DAYONE3 DAYONE2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-x R/W-x YRONE1 YRONE0 bit Bit is unknown R-x R-x MTHONE1 MTHONE0 bit 8 R/W-x R/W-x DAYONE1 DAYONE0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 6-4 SECTEN2:SECTEN0: Binary Coded Decimal Value of Second’s Tens Digit; Contains a value from bit 3-0 SECONE3:SECONE0: Binary Coded Decimal Value of Second’s Ones Digit; Contains a value from © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY U-0 U-0 R/W-x — ...
Page 164
... HRTEN0 HRONE3 HRONE2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-x R/W-x MTHONE1 MTHONE0 bit 8 R/W-x R/W-x DAYONE1 DAYONE0 bit Bit is unknown (1) R/W-x R/W-x WDAY1 WDAY0 bit 8 R/W-x R/W-x HRONE1 HRONE0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 165
... Unimplemented: Read as ‘0’ bit 6-4 SECTEN2:SECTEN0: Binary Coded Decimal Value of Second’s Tens Digit; Contains a value from bit 3-0 SECONE3:SECONE0: Binary Coded Decimal Value of Second’s Ones Digit; Contains a value from © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY R/W-x R/W-x R/W-x ...
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... To avoid a false alarm event, the timer and alarm values should only be changed while the alarm is disabled (ALRMEN = 0 recommended that the ALCFGRPT register and CHIME bit be changed when RTCSYNC = 0. © 2009 Microchip Technology Inc. ...
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... Every 10 minutes 0101 – Every hour 0110 – Every day 0111 – Every week 1000 – Every month (1) 1001 – Every year Note 1: Annually, except when configured for February 29. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY Day of the Week Month Day Hours h ...
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... PIC24FJ128GA010 FAMILY NOTES: DS39747E-page 168 © 2009 Microchip Technology Inc. ...
Page 169
... OUT IN BIT 0 D OUT 1 p_clk © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 19.2 Overview The module implements a software configurable CRC generator. The terms of the polynomial and its length can be programmed using the CRCXOR (X<15:1>) bits and the CRCCON (PLEN3:PLEN0) bits, respectively. ...
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... At least one instruction cycle must pass after a write to CRCWDAT before a read of the VWORD bits is done. 19.3.2 INTERRUPT OPERATION When VWORD4:VWORD0 make a transition from a value of ‘1’ to ‘0’, an interrupt will be generated BIT 12 BIT 15 p_clk p_clk CRC Read Bus CRC Write Bus © 2009 Microchip Technology Inc. ...
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... Denotes the length of the polynomial to be generated minus 1. 19.4 Operation in Power Save Modes 19.4.1 SLEEP MODE If Sleep mode is entered while the module is operating, the module will be suspended in its current state until clock execution resumes. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY R-0 R-0 R-0 VWORD4 VWORD3 VWORD2 ...
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... PIC24FJ128GA010 FAMILY NOTES: DS39747E-page 172 © 2009 Microchip Technology Inc. ...
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... The actual number of analog input pins and external voltage reference input configuration will depend on the specific device. Refer to the device data sheet for further details. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY A block diagram of the A/D Converter is shown in Figure 20-1. ...
Page 174
... V R S/H DAC V INL 10-Bit SAR Data Formatting ADC1BUF0: ADC1BUFF AD1CON1 AD1CON2 AD1CON3 INH AD1CHS AD1PCFG AD1CSSL INL Sample Control Control Logic Input MUX Control Pin Config. Control Internal Data Bus 16 Comparator + R Conversion Logic Conversion Control © 2009 Microchip Technology Inc. ...
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... SAMP: A/D Sample Enable bit 1 = A/D sample/hold amplifier is sampling input 0 = A/D sample/hold amplifier is holding bit 0 DONE: A/D Conversion Status bit 1 = A/D conversion is done 0 = A/D conversion is NOT done © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY U-0 U-0 U-0 — — — ...
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... SMPI1 SMPI0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared External V + pin AV REF AV External V DD External V + pin External V REF U-0 U-0 — — bit 8 R/W-0 R/W-0 BUFM ALTS bit Bit is unknown - pin REF - pin REF SS © 2009 Microchip Technology Inc. ...
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... T (not recommended) AD bit 7-0 ADCS7:ADCS0: A/D Conversion Clock Select bits 11111111 = 256 • ······ 00000001 = 00000000 = T CY © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY R/W-0 R/W-0 R/W-0 SAMC4 SAMC3 SAMC2 R/W-0 R/W-0 R/W-0 ADCS4 ...
Page 178
... Channel 0 positive input is AN0 DS39747E-page 178 U-0 R/W-0 R/W-0 — CH0SB3 CH0SB2 U-0 R/W-0 R/W-0 — CH0SA3 CH0SA2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared - R/W-0 R/W-0 CH0SB1 CH0SB0 bit 8 R/W-0 R/W-0 CH0SA1 CH0SA0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 CSSL15:CSSL0: A/D Input Pin Scan Selection bits 1 = Corresponding analog channel selected for input scan 0 = Analog channel omitted from input scan © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY R/W-0 R/W-0 R/W-0 PCFG12 PCFG11 ...
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... PIN V = Threshold Voltage Leakage Current at the pin due to LEAKAGE various junctions R = Interconnect Resistance Sampling Switch Resistance Sample/Hold Capacitance (from DAC) HOLD ≤ 5 kΩ (Typical HOLD = DAC capacitance = 4.4 pF (Typical negligible if Rs ≤ 5 kΩ. PIN © 2009 Microchip Technology Inc. ...
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... Voltage Level © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY DS39747E-page 181 ...
Page 182
... PIC24FJ128GA010 FAMILY NOTES: DS39747E-page 182 © 2009 Microchip Technology Inc. ...
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... C2IN- C2POS C2IN REF © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY The analog comparators that can be configured in a variety of ways. The inputs can be selected from the analog inputs multiplexed with I/O pins, as well as the on-chip voltage reference. Block diagrams of the various comparator configurations are shown in Figure 21-1 ...
Page 184
... IN IN DS39747E-page 184 R/C-0 R/W-0 R/W-0 C1EVT C2EN C1EN R/W-0 R/W-0 R/W-0 C1INV C2NEG C2POS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 C2OUTEN C1OUTEN bit 8 R/W-0 R/W-0 C1NEG C1POS bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... C1NEG: Comparator 1 Negative Input Configure bit 1 = Input is connected Input is connected to V See Figure 21-1 for the Comparator modes. bit 0 C1POS: Comparator 1 Positive Input Configure bit 1 = Input is connected Input is connected to CV See Figure 21-1 for the Comparator modes. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY + REF ...
Page 186
... PIC24FJ128GA010 FAMILY NOTES: DS39747E-page 186 © 2009 Microchip Technology Inc. ...
Page 187
... DD CVRSS = 0 CVREN CVRR V - REF © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON<5>). The primary difference between the ranges is the size of the steps selected (CVR3:CVR0), with one range offering finer resolution. ...
Page 188
... RSRC RSRC Source Selection bit = V + – RSRC REF REF = AV – AV RSRC DD SS Value Selection 0 ≤ CVR3:CVR0 ≤ 15 bits REF ) RSRC ) RSRC U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 CVR1 CVR0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... The configuration data is automatically loaded from the Flash Configuration Words to the proper Configuration registers during device Resets. Note: Configuration data is reloaded on all types of device resets. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY TABLE 23-1: FLASH CONFIGURATION WORDS LOCATIONS Device ...
Page 190
... R/PO-1 r-1 GWRP DEBUG r R/PO-1 R/PO-1 R/PO-1 FWPSA WDTPS3 WDTPS2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) U-1 U-1 — — bit 16 U-1 R/PO-1 — ICS bit 8 R/PO-1 R/PO-1 WDTPS1 WDTPS0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 191
... Note 1: JTAGEN bit can not be modified using JTAG programming. It can only change using In-Circuit Serial Programming™ (ICSP™). © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY DS39747E-page 191 ...
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... FNOSC2 U-1 U-1 U-1 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /2) OSC U-1 U-1 — — bit 16 R/PO-1 R/PO-1 FNOSC1 FNOSC0 bit 8 R/PO-1 R/PO-1 POSCMD1 POSCMD0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Bit is set bit 23-14 Unimplemented: Read as ‘0’ bit 13-6 FAMID7:FAMID0: Device Family Identifier bits 00010000 = PIC24FJ128GA010 family bit 5-0 DEV5:DEV0: Individual Device Identifier bits 000101 = PIC24FJ64GA006 000110 = PIC24FJ96GA006 000111 = PIC24FJ128GA006 001000 = PIC24FJ64GA008 001001 = PIC24FJ96GA008 001010 = PIC24FJ128GA008 001011 = PIC24FJ64GA010 001100 = PIC24FJ96GA010 001101 = PIC24FJ128GA010 © ...
Page 194
... DOT2:DOT0: Minor Revision Identifier bits DS39747E-page 194 — — — — — — — DOT2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U U — — bit — MAJRV2 bit DOT1 DOT0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... The on-chip regulator is designed to meet the power-up requirements for the device. If the application does not use the regulator, then strict power-up conditions must be adhered to. While powering up, V never exceed V by 0.3 volts. DD © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY FIGURE 23-1: Regulator Enabled (ENVREG tied EFC pins. ...
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... WDT option allows the user to enable the WDT for crit- ical code segments and disable the WDT during non-critical segments for maximum power savings. LPRC Control WDTPS3:WDTPS0 WDT Postscaler Counter 1:1 to 1:32.768 1 ms/4 ms bit. When the FWDTEN Wake from Sleep WDT Overflow Reset © 2009 Microchip Technology Inc. ...
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... The data for the Configuration registers is derived from the Flash Configuration Words in program memory. When the GCP bit is set, the source data for device configuration is also protected as a consequence. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 23.6 In-Circuit Serial Programming Note: This data sheet summarizes the features of this group of PIC24F devices ...
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... PIC24FJ128GA010 FAMILY NOTES: DS39747E-page 198 © 2009 Microchip Technology Inc. ...
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... The bit in the W register or file register (specified by a literal value or indirectly by the contents of register ‘Wb’) © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY The literal instructions that involve data movement may use some of the following operands: • ...
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... Wnd One of 16 source working registers ∈ {W0..W15} Wns WREG W0 (working register used in file register instructions) Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws Source W register ∈ Wso { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } DS39747E-page 200 Description © 2009 Microchip Technology Inc. ...