IC DSPIC MCU/DSP 128K 100-TQFP

DSPIC33FJ128GP310A-I/PT

Manufacturer Part NumberDSPIC33FJ128GP310A-I/PT
DescriptionIC DSPIC MCU/DSP 128K 100-TQFP
ManufacturerMicrochip Technology
SeriesdsPIC™ 33F
DSPIC33FJ128GP310A-I/PT datasheet
 

Specifications of DSPIC33FJ128GP310A-I/PT

Program Memory TypeFLASHProgram Memory Size128KB (128K x 8)
Package / Case100-TFQFPCore ProcessordsPIC
Core Size16-BitSpeed40 MIPs
ConnectivityI²C, IrDA, LIN, SPI, UART/USARTPeripheralsAC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o85Ram Size16K x 8
Voltage - Supply (vcc/vdd)3 V ~ 3.6 VData ConvertersA/D 32x10b/12b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
ProductDSCsData Bus Width16 bit
Processor SeriesDSPIC33FCoredsPIC
Maximum Clock Frequency40 MHzNumber Of Programmable I/os85
Data Ram Size16 KBMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development Tools52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By SupplierPG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033Minimum Operating Temperature- 40 C
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With876-1001 - DSPIC33 BREAKOUT BOARD
Eeprom Size-  
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Page 252/338

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dsPIC33FJXXXGPX06A/X08A/X10A
22.2
On-Chip Voltage Regulator
All of the dsPIC33FJXXXGPX06A/X08A/X10A devices
power their core digital logic at a nominal 2.5V. This
may create an issue for designs that are required to
operate at a higher typical voltage, such as 3.3V. To
simplify
system
design,
all
devices
dsPIC33FJXXXGPX06A/X08A/X10A
porate an on-chip regulator that allows the device to
run its core logic from V
.
DD
The regulator provides power to the core from the
other V
pins. The regulator requires that a
DD
low-ESR (less than 5 ohms) capacitor (such as
tantalum or ceramic) be connected to the V
V
pin (Figure 22-1). This helps to maintain
DDCORE
the stability of the regulator. The recommended
value
for
the
filter
capacitor
is
Table 25-13
of
Section 25.0
Characteristics”.
Note:
It is important for the low-ESR capacitor to
be placed as close as possible to the
V
/V
pin.
CAP
DDCORE
it takes approximately 20 s for the on-chip
,
On a POR
voltage regulator to generate an output voltage. During
this time, designated as T
, code execution is
STARTUP
disabled. T
is applied every time the device
STARTUP
resumes operation after any power-down.
FIGURE 22-1:
CONNECTIONS FOR THE
ON-CHIP VOLTAGE
REGULATOR
3.3V
dsPIC33F
V
DD
V
/V
CAP
DDCORE
C
EFC
V
SS
Note 1:
These are typical operating voltages. Refer to
Section TABLE 25-13: “Internal Voltage
Regulator Specifications” located in
Section 25.1 “DC Characteristics” for the
full operating ranges of V
and V
DD
V
.
DDCORE
2:
It is important for the low-ESR capacitor to be
placed as close as possible to the V
DS70593B-page 252
22.3
BOR: Brown-out Reset
The BOR (Brown-out Reset) module is based on an
internal voltage reference circuit that monitors the
regulated voltage V
the BOR module is to generate a device Reset when a
in
the
brown-out condition occurs. Brown-out conditions are
family
incor-
generally caused by glitches on the AC mains (i.e.,
missing portions of the AC cycle waveform due to bad
power transmission lines or voltage sags due to
excessive current draw when a large inductive load is
turned on).
A BOR will generate a Reset pulse which will reset the
/
device. The BOR will select the clock source, based on
CAP
the device Configuration bit values (FNOSC<2:0> and
POSCMD<1:0>). Furthermore, if an oscillator mode is
provided
in
selected, the BOR will activate the Oscillator Start-up
“Electrical
Timer (OST). The system clock is held until OST
expires. If the PLL is used, then the clock will be held
until the LOCK bit (OSCCON<5>) is ‘1’.
Concurrently, the PWRT time-out (TPWRT) will be
applied before the internal Reset is released. If
TPWRT = 0 and a crystal oscillator is being used, then
a nominal delay of TFSCM = 100 is applied. The total
delay in this case is TFSCM.
The BOR Status bit (RCON<1>) will be set to indicate
that a BOR has occurred. The BOR circuit continues to
operate while in Sleep or Idle modes and will reset the
device should VDD fall below the BOR threshold
voltage.
(1)
/
CAP
/
CAP
Preliminary
/V
. The main purpose of
CAP
DDCORE
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