PIC18F452-I/P Microchip Technology, PIC18F452-I/P Datasheet - Page 177

• Manufacturer Part Number: PIC18F452-I/P
• Description: IC MCU FLASH 16KX16 EE 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F452-I/P

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 34
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: MSSP/SPI/I2C/PSP/USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 40PDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 444-1001 - DEMO BOARD FOR PICMICRO MCUACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: PIC18F452I/P; Q1176145

FIGURE 16-5:
TABLE 16-7:
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
SPBRG
Legend: x = unknown, - = unimplemented locations read as '0'.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits
2002 Microchip Technology Inc.
Name
Note:
RX (pin)
Rcv Shift
Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Shaded cells are not used for Asynchronous Reception.
clear.
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing
the OERR (overrun) bit to be set.
USART Receive Register
Baud Rate Generator Register
GIE/GIEH
PSPIF
PSPIE
PSPIP
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
(1)
(1)
(1)
START
ASYNCHRONOUS RECEPTION
bit
PEIE/
ADIE
ADIP
Bit 6
GIEL
ADIF
RX9
TX9
bit0
TMR0IE INT0IE
bit1
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
CREN ADDEN FERR
SYNC
Bit 4
TXIF
TXIE
TXIP
bit7/8
STOP
bit
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000
SSPIP CCP1IP TMR2IP TMR1IP 0000 0000
RBIE
Bit 3
—
Word 1
RCREG
START
bit
TMR0IF INT0IF
BRGH
Bit 2
bit0
OERR
TRMT
Bit 1
bit7/8 STOP
Word 2
RCREG
RX9D
TX9D
RBIF
Bit 0
bit
START
bit
PIC18FXX2
0000 000x
0000 -00x
0000 0000
0000 -010
0000 0000
POR, BOR
Value on
bit7/8
DS39564B-page 175
STOP
0000 000u
0000 0000
0000 0000
0000 0000
0000 -00x
0000 0000
0000 -010
0000 0000
All Other
bit
Value on
RESETS