PIC18F452-I/P Microchip Technology, PIC18F452-I/P Datasheet - Page 189

• Manufacturer Part Number: PIC18F452-I/P
• Description: IC MCU FLASH 16KX16 EE 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F452-I/P

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 34
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: MSSP/SPI/I2C/PSP/USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 40PDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 444-1001 - DEMO BOARD FOR PICMICRO MCUACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: PIC18F452I/P; Q1176145

17.4
Figure 17-3 shows the operation of the A/D converter
after the GO bit has been set. Clearing the GO/DONE
bit during a conversion will abort the current conver-
sion. The A/D result register pair will NOT be updated
with the partially completed A/D conversion sample.
That is, the ADRESH:ADRESL registers will continue
to contain the value of the last completed conversion
FIGURE 17-3:
17.4.1
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16-bits wide.
The A/D module gives the flexibility to left or right justify
the 10-bit result in the 16-bit result register. The A/D
FIGURE 17-4:
2002 Microchip Technology Inc.
A/D Conversions
T
CY
Set GO bit
Holding capacitor is disconnected from analog input (typically 100 ns)
A/D RESULT REGISTERS
- T
AD
7
Conversion Starts
0000 00
ADRESH
T
b9
AD
A/D CONVERSION T
A/D RESULT JUSTIFICATION
1 T
Right Justified
AD
b8
2 1 0 7
ADFM = 1
2 T
AD
b7
10-bit Result
3 T
ADRESL
AD
b6
Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,
4 T
AD
AD
b5
0
5 T
CYCLES
ADIF bit is set, holding capacitor is connected to analog input.
10-bit Result
AD
b4
6 T
AD
b3
7 T
(or the last value written to the ADRESH:ADRESL reg-
isters). After the A/D conversion is aborted, a 2 T
is required before the next acquisition is started. After
this 2 T
automatically started. The GO/DONE bit can then be
set to start the conversion.
Format Select bit (ADFM) controls this justification.
Figure 17-4 shows the operation of the A/D result justi-
fication. The extra bits are loaded with ’0’s. When an
A/D result will not overwrite these locations (A/D
disable), these registers may be used as two general
purpose 8-bit registers.
Note:
AD
b2
7
8
AD
ADRESH
T
AD
wait, acquisition on the selected channel is
b1
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
10-bit Result
9 T
AD
ADFM = 0
b0
Left Justified
10
0 7 6 5
T
AD
b0
PIC18FXX2
ADRESL
11
0000 00
DS39564B-page 187
0
AD
wait