PIC18F452-I/P Microchip Technology, PIC18F452-I/P Datasheet - Page 190

• Manufacturer Part Number: PIC18F452-I/P
• Description: IC MCU FLASH 16KX16 EE 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F452-I/P

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 34
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: MSSP/SPI/I2C/PSP/USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 40PDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 444-1001 - DEMO BOARD FOR PICMICRO MCUACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: PIC18F452I/P; Q1176145

PIC18FXX2
17.5
An A/D conversion can be started by the “special event
trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as 1011 and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/
DONE bit will be set, starting the A/D conversion, and
the Timer1 (or Timer3) counter will be reset to zero.
Timer1 (or Timer3) is reset to automatically repeat the
A/D acquisition period with minimal software overhead
TABLE 17-2:
DS39564B-page 188
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
ADRESH
ADRESL
ADCON0
ADCON1
PORTA
TRISA
PORTE
LATE
TRISE
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear.
Name
Use of the CCP2 Trigger
PSPIE
PSPIP
PSPIF
A/D Result Register
A/D Result Register
ADCS1
ADFM
GIEH
Bit 7
GIE/
IBF
—
—
—
—
—
—
—
(1)
(1)
(1)
SUMMARY OF A/D REGISTERS
PORTA Data Direction Register
ADCS0
ADCS2
PEIE/
GIEL
ADIF
ADIE
ADIP
Bit 6
OBF
RA6
—
—
—
—
—
TMR0IE
CHS2
RCIE
RCIP
IBOV
RCIF
Bit 5
RA5
—
—
—
—
—
—
PSPMODE
INT0IE
CHS1
TXIE
TXIP
EEIF
EEIE
EEIP
Bit 4
TXIF
RA4
—
—
—
PCFG3
SSPIF
SSPIE
SSPIP
BCLIE
BCLIP
BCLIF
CHS0
RBIE
Bit 3
RA3
—
—
—
PORTE Data Direction bits
GO/DONE
(moving ADRESH/ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition done before the “special
event trigger” sets the GO/DONE bit (starts a
conversion).
If the A/D module is not enabled (ADON is cleared), the
“special event trigger” will be ignored by the A/D
module, but will still reset the Timer1 (or Timer3)
counter.
TMR0IF
CCP1IF
CCP1IE
CCP1IP
PCFG2
LATE2
LVDIF
LVDIE
LVDIP
Bit 2
RA2
RE2
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
PCFG1
INT0IF
LATE1
Bit 1
RA1
RE1
—
TMR1IF
TMR1IE 0000 0000 0000 0000
TMR1IP 0000 0000 0000 0000
CCP2IE
CCP2IP
CCP2IF
PCFG0
LATE0
ADON
RBIF
Bit 0
RA0
RE0
2002 Microchip Technology Inc.
0000 000x 0000 000u
0000 0000 0000 0000
---0 0000 ---0 0000
---0 0000 ---0 0000
---1 1111 ---1 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 00-0 0000 00-0
---- -000 ---- -000
--0x 0000 --0u 0000
--11 1111 --11 1111
---- -000 ---- -000
---- -xxx ---- -uuu
0000 -111 0000 -111
POR, BOR
Value on
All Other
Value on
RESETS