P87C591VFA/00,512 NXP Semiconductors, P87C591VFA/00,512 Datasheet - Page 45

• Manufacturer Part Number: P87C591VFA/00,512
• Description: IC 80C51 MCU 16K OTP 44-PLCC
• Manufacturer: NXP Semiconductors
• Series: 87Cr

Specifications of P87C591VFA/00,512

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: CAN, EBI/EMI, I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: P87C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: CAN, I2C, UART
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-1256-5; 935268182512; P87C591VFAA

Philips Semiconductors
Always if a bus error occurs, the corresponding bus error interrupt is forced, if enabled. In the same time, the current
position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is
fixed until the users software has read out its content once. From now on the capture mechanism is activated again.
The corresponding Interrupt Flag located in the Interrupt Register is cleared during the read access to the Interrupt
Register. A new Bus Error Interrupt is not possible until the Capture Register is read out once.
12.5.14 E
The Error Warning Limit could be defined within this register. The default value (after hardware reset) is 96d. In Reset
Mode this register appears to the CPU as a read / write memory.
Table 28 Error Warning Limit Register (EWLR) (CAN address 13)
Note that a content change of the EWL-Register is possible only, if the Reset Mode was entered previously. An Error
Status change (Status Register) and an Error Warning Interrupt forced by the new register content will not occur, until
the Reset Mode is cancelled again.
12.5.15 RX E
The RX Error Counter Register reflects the current value of the Receive Error Counter. After hardware reset this register
is initialised to “0”. In Operating Mode this register appears to the CPU as a read only memory. A write access to this
register is possible only in Reset Mode.
If a Bus Off event occurs, the RX Error counter is initialised to “0”. As long as Bus Off is valid, writing to this register has
no effect.
Table 29 RX Error Counter Register (RXERR) (CAN address 14)
Note that a CPU-forced content change of the RX Error Counter is possible only, if the Reset Mode was entered
previously. An Error Status change (Status Register), an Error Warning or an Error Passive Interrupt forced by the new
register content will not occur, until the Reset Mode is cancelled again.
2000 Jul 26
RXERR.7
Single-chip 8-bit microcontroller with CAN controller
EWL.7
7
7
RROR
RROR
RXERR.6
W
EWL.6
ARNING
C
6
6
OUNTER
L
IMIT
R
RXERR.5
R
EGISTER
EWL.5
EGISTER
5
5
(RXERR)
(EWLR)
RXERR.4
EWL.4
4
4
45
RXERR.3
EWL.3
3
3
RXERR.2
EWL.2
2
2
RXERR.1
EWL.1
Preliminary Specification
1
1
P8xC591
RXERR.0
EWL.0
0
0