LPC2294HBD144/01,5 NXP Semiconductors, LPC2294HBD144/01,5 Datasheet
LPC2294HBD144/01,5
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LPC2294HBD144/01-S
LPC2294HBD144/01-S
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LPC2294HBD144/01,5 Summary of contents
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LPC2292/LPC2294 16/32-bit ARM microcontrollers; 256 kB ISP/IAP flash with CAN, 10-bit ADC and external memory interface Rev. 7 — 4 December 2008 1. General description The LPC2292/LPC2294 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded ...
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... NXP Semiconductors on-chip static RAM and 256 kB on-chip flash program memory. 128-bit wide interface/accelerator enables high-speed 60 MHz operation. I In-System Programming/In-Application Programming (ISP/IAP) via on-chip bootloader software. Single flash sector or full chip erase in 400 ms and programming of 256 ms. I EmbeddedICE-RT and Embedded Trace interfaces offer real-time debugging with the on-chip RealMonitor software as well as high-speed real-time tracing of instruction execution ...
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... NXP Semiconductors Table 1. Type number LPC2294HBD144 LPC2294HBD144/00 LPC2294HBD144/01 3.1 Ordering options Table 2. Type number LPC2292FBD144 LPC2292FBD144/00 256 kB LPC2292FBD144/01 256 kB LPC2292FET144/00 256 kB LPC2292FET144/01 256 kB LPC2292FET144/G LPC2294HBD144 LPC2294HBD144/00 256 kB LPC2294HBD144/01 256 kB LPC2292_2294_7 Product data sheet 16/32-bit ARM microcontrollers with external memory interface Ordering information … ...
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... NXP Semiconductors 4. Block diagram LPC2292 LPC2294 HIGH-SPEED (4) P0, P1 GPIO 48 PINS TOTAL ARM7 local bus INTERNAL SRAM CONTROLLER 16 kB SRAM EXTERNAL EINT3 to EINT0 INTERRUPTS 4 CAP0 CAPTURE/ 4 CAP1 COMPARE 4 MAT0 TIMER 0/TIMER 1 4 MAT1 AIN3 to AIN0 A/D CONVERTER AIN7 to AIN4 P0[30:0] P1[31:16], P1[1:0] ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning (1) Pin configuration is identical for devices with and without /00 and /01 suffixes. Fig 2. LQFP144 pinning (1) Pin configuration is identical for devices with and without /00 and /01 suffixes. Fig 3. TFBGA144 pinning LPC2292_2294_7 Product data sheet 16/32-bit ARM microcontrollers with external memory interface ...
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Table 3. Ball allocation Row Column P2[22]/ V P1[28]/ P2[21]/ DDA(1V8) D22 TDI D21 B V P1[27]/ XTAL2 V DD(3V3) SSA(PLL) TDO C P0[21]/ V XTAL1 V SS SSA PWM5/ CAP1[3] D P0[24]/ P1[19]/ P0[23]/ ...
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Table 3. Ball allocation …continued Row Column P0[29]/ P0[30]/ P1[16]/ P0[0]/ AIN2/ AIN3/ TRACE TXD0/ CAP0[3]/ EINT3/ PKT0 PWM1 MAT0[3] CAP0[0] M P3[25]/ P3[24]/ V P1[31]/ DD(3V3) CS2 CS3 TRST P3[23]/ P3[21]/ ...
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... NXP Semiconductors 5.2 Pin description Table 4. Pin description Symbol Pin (LQFP) P0[0] to P0[31] [2] P0[0]/TXD0/ 42 PWM1 [4] P0[1]/RXD0/ 49 PWM3/EINT0 [5] P0[2]/SCL/ 50 CAP0[0] [5] P0[3]/SDA/ 58 MAT0[0]/EINT1 [2] P0[4]/SCK0/ 59 CAP0[1] [2] P0[5]/MISO0/ 61 MAT0[1] [2] P0[6]/MOSI0/ 68 CAP0[2] [4] P0[7]/SSEL0/ 69 PWM2/EINT2 [2] P0[8]/TXD1/ 75 PWM4 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin (LQFP) [2] P0[12]/DSR1/ 84 MAT1[0]/RD4 [2] P0[13]/DTR1/ 85 MAT1[1]/TD4 [4] P0[14]/DCD1/ 92 EINT1 [4] P0[15]/RI1/ 99 EINT2 [4] P0[16]/EINT0/ 100 MAT0[2]/ CAP0[2] [2] P0[17]/CAP1[2]/ 101 SCK1/MAT1[2] [2] P0[18]/CAP1[3]/ 121 MISO1/MAT1[3] [2] P0[19]/MAT1[2]/ 122 MOSI1/CAP1[2] [4] P0[20]/MAT1[3]/ ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin (LQFP) [6] P0[27]/AIN0/ 23 CAP0[1]/ MAT0[1] [6] P0[28]/AIN1/ 25 CAP0[2]/ MAT0[2] [6] P0[29]/AIN2/ 32 CAP0[3]/ MAT0[3] [6] P0[30]/AIN3/ 33 EINT3/CAP0[0] P1[0] to P1[31] [7] P1[0]/CS0 91 [7] P1[1]/OE 90 [7] P1[16]/ 34 TRACEPKT0 [7] P1[17]/ 24 TRACEPKT1 [7] P1[18]/ 15 TRACEPKT2 [7] P1[19]/ 7 TRACEPKT3 [7] P1[20]/ 102 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin (LQFP) [7] P1[25]/EXTIN0 60 [7] P1[26]/RTCK 52 [7] P1[27]/TDO 144 [7] P1[28]/TDI 140 [7] P1[29]/TCK 126 [7] P1[30]/TMS 113 [7] P1[31]/TRST 43 P2[0] to P2[31] [7] P2[0]/D0 98 [7] P2[1]/D1 105 [7] P2[2]/D2 106 [7] P2[3]/D3 108 [7] P2[4]/D4 109 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin (LQFP) [7] P2[24]/D24 11 [7] P2[25]/D25 12 [7] P2[26]/D26/ 13 BOOT0 [7] P2[27]/D27/ 16 BOOT1 [7] P2[28]/D28 17 [7] P2[29]/D29 18 [6] P2[30]/D30/ 19 AIN4 [6] P2[31]/D31/ 20 AIN5 P3[0] to P3[31] [7] P3[0]/A0 89 [7] P3[1]/A1 88 [7] P3[2]/A2 87 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin (LQFP) [7] P3[17]/A17 48 [7] P3[18]/A18 47 [7] P3[19]/A19 46 [7] P3[20]/A20 45 [7] P3[21]/A21 44 [7] P3[22]/A22 41 [7] P3[23]/A23/ 40 XCLK [7] P3[24]/CS3 36 [7] P3[25]/CS2 35 [7] P3[26]/CS1 30 [7] P3[27]/WE 29 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin (LQFP) V 143 DDA(1V8 31, 39, 51, DD(3V3) 57, 77, 94, 104, 112, 119 V 14 DDA(3V3) [1] LPC2294 only. [ tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. [3] SSP interface available on LPC2292/2294/01 only. ...
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... NXP Semiconductors 6. Functional description 6.1 Architectural overview The ARM7TDMI general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on RISC principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed CISC. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core ...
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... NXP Semiconductors 6.3 On-chip SRAM On-chip SRAM may be used for code and/or data storage. The SRAM may be accessed as 8-bit, 16-bit, and 32-bit. The LPC2292/LPC2294 provide SRAM. 6.4 Memory map The LPC2292/LPC2294 memory maps incorporate several distinct regions, as shown in Figure 4. In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either fl ...
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... NXP Semiconductors 6.5 Interrupt controller The VIC accepts all of the interrupt request inputs and categorizes them as Fast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. ...
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... NXP Semiconductors Table 5. Block UART1 PWM0 I2C SPI0 SPI1 and SSP PLL RTC System Control ADC CAN [1] SSP interface and UART0/1 auto-baud control are available on LPC2292/2294/01 only. 6.6 Pin connect block The pin connect block allows selected pins of the microcontroller to have more than one function. Confi ...
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... NXP Semiconductors 6.8 General purpose parallel I/O (GPIO) and Fast I/O Device pins that are not connected to a specific peripheral function are controlled by the parallel I/O registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back, as well as the current state of the port pins ...
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... NXP Semiconductors 6.10 CAN controllers and acceptance filter The LPC2292/LPC2294 each contain two/four CAN controllers. The CAN is a serial communications protocol which efficiently supports distributed real-time control with a very high level of security. Its domain of application ranges from high-speed networks to low cost multiplex wiring. ...
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... NXP Semiconductors capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I controlled by more than one bus master connected to it. 2 The I C-bus implemented in LPC2292/LPC2294 supports bit rate up to 400 kbit/s (Fast ...
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... NXP Semiconductors 6.14 SSP controller (LPC2292/94/01 only) The SSP is a controller capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. Data transfers are in principle full duplex, with frames of four to 16 bits of data fl ...
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... NXP Semiconductors 6.15.2 Features available in LPC2292/LPC2294/01 only The LPC2292/LPC2294/01 can count external events on one of the capture inputs if the external pulse lasts at least one half of the period of the PCLK. In this configuration, unused capture lines can be selected as regular timer capture inputs, or used as external interrupts. • ...
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... NXP Semiconductors 6.18 Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2292/LPC2294. The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions when specifi ...
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... NXP Semiconductors • Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. Software must ‘release’ new match values before they can become effective. • May be used as a standard timer if the PWM mode is not enabled. • A 32-bit Timer/Counter with a programmable 32-bit prescaler. ...
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... NXP Semiconductors The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. When power is applied to the chip, or some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on ...
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... NXP Semiconductors 6.19.7 Power control The LPC2292/LPC2294 support two reduced power modes: Idle mode and Power-down mode. In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses ...
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... NXP Semiconductors communication channel allows the JTAG port to be used for sending and receiving data without affecting the normal program flow. The debug communication channel data and control registers are mapped in to addresses in the EmbeddedICE logic. The JTAG clock (TCK) must be slower than interface to operate ...
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... NXP Semiconductors 7. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (1.8 V) DD(1V8) V supply voltage (3.3 V) DD(3V3) V analog supply voltage (3.3 V) DDA(3V3) V analog input voltage IA V input voltage I I supply current DD I ground current ...
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... NXP Semiconductors 8. Static characteristics Table 7. Static characteristics +125 C, unless otherwise specified. amb Symbol Parameter V supply voltage (1.8 V) DD(1V8) V supply voltage (3.3 V) DD(3V3) V analog supply voltage DDA(3V3) (3.3 V) Standard port pins, RESET, RTCK I LOW-level input current IL I HIGH-level input current IH I OFF-state output current ...
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... NXP Semiconductors Table 7. Static characteristics +125 C, unless otherwise specified. amb Symbol Parameter I Power-down mode supply DD(pd) current Power consumption LPC2292/01 and LPC2294/01 I active mode supply current V DD(act) I Idle mode supply current DD(idle) I Power-down mode supply DD(pd) current 2 I C-bus pins ...
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... NXP Semiconductors Table 7. Static characteristics +125 C, unless otherwise specified. amb Symbol Parameter Oscillator pins V input voltage on pin XTAL1 i(XTAL1) V output voltage on pin o(XTAL2) XTAL2 [1] Typical ratings are not guaranteed. The values listed are at room temperature (+25 C), nominal supply voltages. [2] Internal rail. ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 5. ADC characteristics LPC2292_2294_7 Product data sheet ...
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... NXP Semiconductors 8.1 Power consumption measurements for LPC2292/01 and LPC2294/01 The power consumption measurements represent typical values for the given conditions. The peripherals were enabled through the PCONP register, but for these measurements, the peripherals were not configured to run. Peripherals were disabled through the PCONP register ...
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... NXP Semiconductors 45 I DD(act) (mA -40 -15 Test conditions: Active mode entered executing code on-chip flash; PCLK = core voltage 1.8 V; all peripherals disabled. Fig 8. Typical LPC2292/01 I DD(act) 10.0 I DD(idle) (mA) 8.0 all peripherals enabled 6.0 all peripherals disabled 4.0 2.0 0 Test conditions: Idle mode entered executing code from on-chip flash; PCLK = ...
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... NXP Semiconductors 10.0 I DD(idle) (mA) 8.0 6.0 4.0 2.0 1.65 Test conditions: Idle mode entered executing code from on-chip flash; PCLK = all peripherals enabled but not active. amb Fig 10. Typical LPC2292/01 I DD(idle) 6.0 I DD(idle) (mA) 5.0 4.0 3.0 2.0 1.0 -40 -15 Test conditions: Idle mode entered executing code from on-chip flash; PCLK = Core voltage 1.8 V ...
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... NXP Semiconductors 200 I DD(pd 160 120 -40 -15 Test conditions: Power-down mode entered executing code from on-chip flash. Fig 12. Typical LPC2292/01 core power-down current I 50.0 I DD(act) (mA) 40.0 30.0 20.0 10.0 0 Test conditions: Active mode entered executing code from on-chip flash; PCLK = core voltage 1.8 V. ...
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... NXP Semiconductors 55.0 I DD(act) (mA) 45.0 35.0 25.0 15.0 5.0 1.65 Test conditions: Active mode entered executing code from on-chip flash; PCLK = all peripherals enabled but not active. amb Fig 14. Typical LPC2294/01 I DD(act) 45.0 I DD(act) (mA) 35.0 25.0 15.0 5.0 -40 -25 -10 Test conditions: Active mode entered executing code from on-chip flash; PCLK = core voltage 1.8 V ...
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... NXP Semiconductors 15.0 I DD(idle) (mA) 10.0 5.0 0 Test conditions: Idle mode entered executing code from on-chip flash; PCLK = core voltage 1.8 V. amb Fig 16. Typical LPC2294/01 I DD(idle) 15.0 I DD(idle) (mA) 10.0 5.0 0.0 1.65 Test conditions: Idle mode entered executing code from on-chip flash; PCLK = ...
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... NXP Semiconductors 6.50 I DD(idle) (mA) 5.50 4.50 3.50 2.50 1.50 0.50 -40 -25 -10 Test conditions: Idle mode entered executing code from on-chip flash; PCLK = core voltage 1.8 V; all peripherals disabled. Fig 18. Typical LPC2294/01 I DD(idle) 500 I DD(pd 400 300 200 100 0 -40 -25 -10 Test conditions: Power-down mode entered executing code from on-chip flash. ...
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... NXP Semiconductors 45.0 I DD(act) 60 MHz (mA) 35.0 48 MHz 25.0 15.0 12 MHz 5.0 1.65 Test conditions: Active mode entered executing code from on-chip flash; PCLK = all peripherals disabled. amb Fig 20. Typical LPC2292/01 and LPC2294/01 I 10.0 I DD(idle) (mA) 5.0 0.0 1.65 Test conditions: Idle mode entered executing code from on-chip flash; PCLK = ...
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... NXP Semiconductors Table 9. Core voltage 1 Peripheral PWM0 2 I C-bus SPI0/1 RTC PCEMC ADC CAN1/2 Table 10. Core voltage 1 Peripheral Timer0 Timer1 UART0 UART1 PWM0 2 I C-bus SPI0/1 RTC PCEMC ADC CAN1/2/3/4 9. Dynamic characteristics Table 11. Dynamic characteristics +125 C; V amb DD(1V8) Symbol Parameter ...
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... NXP Semiconductors Table 11. Dynamic characteristics +125 C; V amb DD(1V8) Symbol Parameter t clock rise time CLCH t clock fall time CHCL Port pins (except P0[2] and P0[3]) t rise time r t fall time C-bus pins (P0[2] and P0[3]) t fall time f [1] Parameters are valid over operating temperature range unless otherwise specified. ...
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... NXP Semiconductors Table 12. External memory interface dynamic characteristics pF amb Symbol Parameter Common to read and write cycles t XCLK HIGH to address valid CHAV time t XCLK HIGH to CS LOW time CHCSL t XCLK HIGH to CS HIGH CHCSH time t XCLK HIGH to address CHANV invalid time Read cycle parameters ...
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... NXP Semiconductors Table 12. External memory interface dynamic characteristics pF amb Symbol Parameter t BLS HIGH to data invalid BLSHDNV time t XCLK HIGH to data valid CHDV time t XCLK HIGH to WE LOW CHWEL time t XCLK HIGH to BLS LOW CHBLSL time t XCLK HIGH to WE HIGH CHWEH time ...
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... NXP Semiconductors 9.1 Timing XCLK CS addr data t CSLOEL OE Fig 22. External memory read access XCLK CS BLS/WE addr data OE Fig 23. External memory write access LPC2292_2294_7 Product data sheet 16/32-bit ARM microcontrollers with external memory interface t CSLAV OELAV t CHOEL t CSLDV t AVCSL t WELWEH t CSLWEL t BLSLBLSH ...
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... NXP Semiconductors Fig 24. External clock timing (with an amplitude of at least V LPC2292_2294_7 Product data sheet LPC2292/LPC2294 16/32-bit ARM microcontrollers with external memory interface t CHCX CHCL CLCX CLCH T cy(clk) = 200 mV) i(RMS) Rev. 7 — 4 December 2008 002aaa907 © NXP B.V. 2008. All rights reserved. ...
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... NXP Semiconductors 10. Package outline LQFP144: plastic low profile quad flat package; 144 leads; body 1 108 109 pin 1 index 144 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 0.27 mm 1.6 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors TFBGA144: plastic thin fine-pitch ball grid array package; 144 balls ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) UNIT max 1.20 0.40 0.80 mm nom 1.05 0.35 0.70 min 0.95 0.30 0.65 OUTLINE VERSION IEC SOT569-2 Fig 26. Package outline SOT569-2 (TFBGA144) ...
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... NXP Semiconductors 11. Abbreviations Table 14. Acronym ADC AHB AMBA APB CAN CISC FIFO GPIO I/O JTAG LSB PLL PWM RISC SPI SRAM SSI SSP TTL UART LPC2292_2294_7 Product data sheet 16/32-bit ARM microcontrollers with external memory interface Acronym list Description Analog-to-Digital Converter ...
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... NXP Semiconductors 12. Revision history Table 15. Revision history Document ID Release date LPC2292_2294_7 20081204 • Modifications: Figure 1 “Block • Figure 24 “External clock timing (with an amplitude of at least V figure note row “V • Table 4 “Pin P3[31]. • Table 5 “Interrupt • Table 7 “Static • ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 15. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 Key features brought by LPC2292/ LPC2294/01 devices 2.2 Key features common for all devices . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 Functional description . . . . . . . . . . . . . . . . . . 15 6 ...