Z16F2810AG20SG Zilog, Z16F2810AG20SG Datasheet - Page 107

• Manufacturer Part Number: Z16F2810AG20SG
• Description: IC ZNEO MCU FLASH 128K 64LQFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2810AG20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-LQFP
• Processor Series: Z16F2x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4535

Table 51. IRQ1 Enable High Bit Register (IRQ1ENH)
Table 52. IRQ1 Enable Low Bit Register (IRQ1ENL)
PS022008-0810
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
IRQ1 Enable High and Low Bit Registers
PAD7ENH PAD6ENH PAD5ENH PAD4ENH PAD3ENH PAD2ENH PAD1ENH PAD0ENH
PAD7ENL PAD6ENL PAD5ENL PAD4ENL PAD3ENL PAD2ENL PAD1ENL PAD0ENL
R/W
R/W
7
0
7
0
The IRQ1 enable high and low bit registers (see
encoded enabling for interrupts in the interrupt request 1 register. Priority is generated by
setting bits in each register.
Table 50. IRQ1 Enable and Priority Encoding
PADxENH—Port A/D Bit[x] Interrupt Request Enable High Bit.
PAxENL—Port A/D Bit[x] Interrupt Request Enable Low Bit.
IRQ1ENH[x]
0
0
1
1
Note: x indicates the register bits from 0 through 7.
R/W
R/W
6
0
6
0
IRQ1ENL[x] Priority
R/W
R/W
0
1
0
1
5
5
0
0
P R E L I M I N A R Y
Table 50
Disabled
Level 1
Level 2
Level 3
R/W
R/W
4
0
4
0
FF_E036H
FF_E037H
describes the priority control for IRQ1.
R/W
R/W
3
3
0
0
Table 51
Description
Disabled
Low
Nominal
High
and
R/W
R/W
2
0
2
0
Table
Product Specification
ZNEO
52) form a priority
R/W
R/W
Interrupt Controller
1
1
0
0
Z16F Series
R/W
R/W
0
0
0
0
92