Z16F2810AG20SG Zilog, Z16F2810AG20SG Datasheet - Page 108

• Manufacturer Part Number: Z16F2810AG20SG
• Description: IC ZNEO MCU FLASH 128K 64LQFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2810AG20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-LQFP
• Processor Series: Z16F2x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4535

Table 54. IRQ2 Enable High Bit Register (IRQ2ENH)
PS022008-0810
BITS
FIELD
RESET
R/W
ADDR
IRQ2 Enable High and Low Bit Registers
PWMTENH
R/W
7
0
The IRQ2 enable high and low bit registers (see
encoded enabling for interrupts in the interrupt request 2 register. Priority is generated by
setting bits in each register.
Table 53. IRQ2 Enable and Priority Encoding
PWMTENH—PWM Timer Interrupt Request Enable High Bit
U1RENH—UART 1 Receive Interrupt Request Enable High Bit
U1TENH—UART 1 Transmit Interrupt Request Enable High Bit
PWMFENH— PWM Fault Interrupt Request Enable High Bit
CxENH/DMAxENH—Port Cx or DMAx Interrupt Request Enable High Bit
IRQ2ENH[x]
0
0
1
1
Note: x indicates the register bits from 0 through 7.
U1RENH
R/W
6
0
U1TENH
IRQ2ENL[x]
R/W
5
0
0
1
0
1
P R E L I M I N A R Y
Table 53
PWMFENH
R/W
4
0
Priority
Disabled
Level 1
Level 2
Level 3
FF_E03AH
describes the priority control for IRQ2.
DMA3ENH
C3ENH/
R/W
3
0
Table 54
Description
Disabled
Low
Nominal
High
DMA2ENH
C2ENH/
R/W
and
2
0
Table
Product Specification
ZNEO
DMA1ENH
C1ENH/
55) form a priority
R/W
Interrupt Controller
1
0
Z16F Series
DMA0ENH
C0ENH/
R/W
0
0
93