Z16F2810AG20SG Zilog, Z16F2810AG20SG Datasheet - Page 225

• Manufacturer Part Number: Z16F2810AG20SG
• Description: IC ZNEO MCU FLASH 128K 64LQFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2810AG20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-LQFP
• Processor Series: Z16F2x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4535

PS022008-0810
Software Control of I
Master Transactions
The I
MODE[1:0]
Master/Slave or Slave only mode and configures the slave for 7-bit or 10-bit addressing
recognition. The baud rate High and Low Byte Registers must be programmed for the I
baud rate in slave mode as well as in master mode. In slave mode, the baud rate value
programmed must match the master's baud rate within +/- 25% for proper operation.
MASTER/SLAVE mode is used for:
•
•
•
In Slave-only mode the
initiate a master transaction by accident). This restricts the operation to slave only mode
and prevents accidental operation in master mode.
Software controls I
controller or by polling the I
To use interrupts, the I
followed by executing an
set to enable transmit interrupts. An I
Status register to determine the cause of the interrupt.
To control transactions by polling, the interrupt bits (TDRE, RDRF, SAM, ARBLST,
SPRS, and NCKI) in the I
regardless of the state of the TXI bit.
The following sections describe the Master read and write transactions to both 7- and 
10-bit Slaves.
Master Arbitration
If a Master loses arbitration during the address byte, it releases the SDA line, switches to
SLAVE mode and monitors the address to determine if it is selected as a Slave. If a Master
loses arbitration during a transmit data byte, it releases the SDA line and waits for the next
STOP or START condition.
The Master detects a loss of arbitration when a 1 is transmitted but a 0 is received from the
bus in the same bit time. This loss occurs if more than one Master is simultaneously
accessing the bus. Loss of arbitration occurs during the address phase (two or more
Masters accessing different Slaves) or during the data phase when the Masters are
attempting to write different data to the same Slave.
Master only operation in a single master, one or more slave I
Master/Slave in a multi-master, multi-slave I
Slave only operation in an I
2
C Controller is configured using the I
field of the I
2
2
C Transactions
C transactions by enabling the I
2
C interrupt must be enabled in the Interrupt Controller and
START
2
EI
2
C Mode register allows configuring the I
P R E L I M I N A R Y
C Status register must be polled. The
2
instruction. The TXI bit in the I
C Status register.
2
bit of the I
C system.
2
C interrupt service routine then verifies the I
2
C Control register is ignored (software cannot
2
C Control and I
2
C system.
2
C Controller interrupt in the interrupt
2
2
C Mode registers. The
C Control register must be
I
2
2
C Master/Slave Controller
Product Specification
TDRE
C system.
ZNEO
2
C Controller for
bit asserts
Z16F Series
2
C
2
C
209