Z16F2810AG20SG Zilog, Z16F2810AG20SG Datasheet - Page 241

• Manufacturer Part Number: Z16F2810AG20SG
• Description: IC ZNEO MCU FLASH 128K 64LQFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2810AG20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-LQFP
• Processor Series: Z16F2x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4535

PS022008-0810
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Slave Write Transaction with Data DMA
In a transaction where the I
master, the software must set the
the reception of the last byte. As in the Master Read transaction described above, the
watermark DMA interrupt is used to notify software when the N-1st byte has been
received.
•
•
•
•
•
•
The I
The I
The I
When the first DMA interrupt occurs indicating the (N-1)st byte has been received, the
Set the
The DMA transfers the data to memory as it is received from the slave.
When the second DMA interrupt occurs, it indicates that the Nth byte has been
Clear the
The I
When the SAM interrupt occurs, set the
The DMA transfers the data to memory as it is received from the master.
When the first DMA interrupt occurs indicating that the (N-1)st byte is received, the
error conditions. A Not Acknowledge interrupt occurs on the last byte transferred.
master mode transactions. The
section, using the
slave acknowledges. Do not set the STOP bit unless
acknowledge).
NAK
received. Set the STOP bit in the I2CCTL register. The STOP bit is polled by software
to determine when the transaction is actually completed.
Configure the selected DMA channel for I
DMACTL register for the last buffer to be transferred. Typically one buffer will be
defined with a transfer length of N where N bytes are expected to be received from the
master. The watermark is set to 1 by writing a 0x01 to DMAxLAR[23:16].
error conditions.
Slave mode transactions. The
NAK
Initiate the I
2
bit must be set in the I2CCTL register.
2
bit must be set in the I2CCTL register.
2
2
C interrupt must be enabled in the interrupt controller to alert software of any I
C interrupt must be enabled in the interrupt controller to alert software of any I
C Master/Slave must be configured as defined in the sections above describing
C Master/Slave must be configured as defined in the sections above describing
DMAIF
DMAIF
2
C transaction as described in the
bit in the I2CMODE register.
bit in the I2CMODE register.
ACKV
P R E L I M I N A R Y
2
and
C Master/Slave operates as a slave, receiving data written by a
ACK
NAK
TXI
TXI
bits in the I2CSTATE register to determine if the
bit after the N-1st byte has been received or during
bit in the I2CCTL register must be cleared.
bit in the I2CCTL register must be cleared.
DMAIF
2
C receive. The
Master Address Only Transactions
bit in the I2CMODE register.
ACKV
=1 and
I
IEOB
2
C Master/Slave Controller
Product Specification
ZNEO
ACK
bit must be set in the
=0 (slave did not
Z16F Series
2
2
C
C
225