ST92F150CV1TB STMicroelectronics, ST92F150CV1TB Datasheet - Page 304

• Manufacturer Part Number: ST92F150CV1TB
• Description: MCU 8BIT 128K FLASH 100TQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150CV1TB

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, EBI/EMI, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4883

J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
10.9.7 Register Description
The JBLPD peripheral uses 48 registers that are
mapped in a single page of the ST9 register file.
Twelve registers are mapped from R240 (F0h) to
R251 (FBh): these registers are usually used to
control the JBLPD. See
Stacked Registers
these registers.
Thirty-six registers are mapped from R252 (FCh)
to R255 (FFh). This is obtained by creating 9 sub-
pages, each containing 4 registers, mapped in the
same register addresses; 4 bits (RSEL[3:0]) of a
Figure 141. JBLPD Register Map
304/429
9
R241 (F1h)
R242 (F2h)
R243 (F3h)
R245 (F5h)
R246 (F6h)
R247 (F7h)
R249 (F9h)
R250 (FAh)
R251 (FBh)
R253 (FDh)
R254 (FEh)
R255 (FFh)
R240 (F0h)
R244 (F4h)
R248 (F8h)
R252 (FCh)
STATUS
PRLR
TXDATA
RXDATA
TXOP
CLKSEL
CONTROL
PADDR
ERROR
IVR
IMR
OPTIONS
CREG0
CREG1
CREG2
CREG3
for a detailed description of
Section 10.9.7.1 Un-
RDAPR
RDCPR
TDAPR
TDCPR
FREG0
FREG1
FREG2
FREG3
FREG4
FREG5
FREG6
FREG7
register (OPTIONS) are used to select the current
sub-page. See
ters
isters.
The ST9 Register File page used is 23 (17h).
NOTE: Bits marked as “Reserved” should be left at
their reset value to guarantee software compatibil-
ity with future versions of the JBLPD.
FREG8
FREG9
FREG10
FREG11
section for a detailed description of these reg-
FREG12
FREG13
FREG14
FREG15
Section 10.9.7.2 Stacked Regis-
FREG16
FREG17
FREG18
FREG19
FREG20
FREG21
FREG22
FREG23
FREG24
FREG25
FREG26
FREG27
FREG29
FREG28
FREG30
FREG31