ST92F150CV1TB STMicroelectronics, ST92F150CV1TB Datasheet - Page 350

• Manufacturer Part Number: ST92F150CV1TB
• Description: MCU 8BIT 128K FLASH 100TQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150CV1TB

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, EBI/EMI, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4883

CONTROLLER AREA NETWORK (bxCAN)
CONTROLLER AREA NETWORK (Cont’d)
10.10.8.2 Mailbox Registers
This chapter describes the registers of the transmit
and receive mailboxes. Refer to
Message Storage
Transmit and receive mailboxes have the same
registers except:
– MCSR register in a transmit mailbox is replaced
– A receive mailbox is always write protected.
– A transmit mailbox is write enable only while
MAILBOX CONTROL STATUS REGISTER
(MCSR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7:6 = Reserved. Forced to 0 by hardware.
Bit 5 = TERR Transmission Error
- Read/Clear
This bit is updated by hardware after each trans-
mission attempt.
0: The previous transmission was successful
1: The previous transmission failed due to an error
Bit 4 = ALST Arbitration Lost
- Read/Clear
This bit is updated by hardware after each trans-
mission attempt.
0: The previous transmission was successful
1: The previous transmission failed due to an arbi-
350/429
9
by MFMI register in a receive mailbox.
empty, corresponding TME bit in the CTPR reg-
ister set.
tration lost
7
0
0
TERR
for detailed register mapping.
ALST
TXOK RQCP ABRQ TXRQ
Section 10.10.5.5
0
Bit 3 = TXOK Transmission OK
- Read/Clear
The hardware updates this bit after each transmis-
sion attempt.
0: The previous transmission failed
1: The previous transmission was successful
Note: This bit has the same value as the corre-
sponding TXOKx bit in the CTSR register.
Bit 2 = RQCP Request Completed
- Read/Clear
Set by hardware when the last request (transmit or
abort) has been performed.
Cleared by software writing a “1” or by hardware
on transmission request.
Note: This bit has the same value as the corre-
sponding RQCPx bit of the CTSR register.
Clearing this bit clears all the status bits (TX-
OK, ALST and TERR) in the MCSR register and
the RQCP and TXOK bits in the CTSR register.
Bit 1 = ABRQ Abort Request for Mailbox
- Read/Set
Set by software to abort the transmission request
for the corresponding mailbox.
Cleared by hardware when the mailbox becomes
empty.
Setting this bit has no effect when the mailbox is
not pending for transmission.
Bit 0 = TXRQ Transmit Mailbox Request
- Read/Set
Set by software to request the transmission for the
corresponding mailbox.
Cleared by hardware when the mailbox becomes
empty.
Note: This register is implemented only in transmit
mailboxes. In receive mailboxes, the MFMI regis-
ter is mapped at this location.