MCHC908QY1CDWE Freescale Semiconductor, MCHC908QY1CDWE Datasheet - Page 29

• Manufacturer Part Number: MCHC908QY1CDWE
• Description: IC MCU 1.5K FLASH 16-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908QY1CDWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 1.5KB (1.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Processor Series: HC08QY
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
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Addr.
↓
TIM Counter Register Low
TIM Channel 0 Status and
TIM Channel 1 Status and
Oscillator Status Register
Control Register (TSC0)
Control Register (TSC1)
Register High (TMODH)
Oscillator Trim Register
Register High (TCH0H)
Register High (TCH1H)
Register Low (TMODL)
Register Low (TCH0L)
Register Low (TCH1L)
Register Name
TIM Counter Modulo
TIM Counter Modulo
Unimplemented
Unimplemented
TIM Channel 0
TIM Channel 0
TIM Channel 1
TIM Channel 1
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(OSCSTAT)
(OSCTRIM)
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 5)
(TCNTL)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
MC68HC908QY/QT Family Data Sheet, Rev. 6
TRIM7
CH0F
CH1F
Bit 15
Bit 15
Bit 15
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
R
0
1
1
0
0
0
0
0
1
= Unimplemented
CH0IE
CH1IE
TRIM6
Bit 14
Bit 14
Bit 14
Bit 6
Bit 6
Bit 6
Bit 6
R
6
0
1
1
0
0
0
0
TRIM5
MS0B
Bit 13
Bit 13
Bit 13
Bit 5
Bit 5
Bit 5
Bit 5
R
5
0
1
1
0
0
0
0
0
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
TRIM4
MS0A
MS1A
Bit 12
Bit 12
Bit 12
Bit 4
Bit 4
Bit 4
Bit 4
R
R
4
0
1
1
0
0
0
0
= Reserved
ELS0B
ELS1B
TRIM3
Bit 11
Bit 11
Bit 11
Bit 3
Bit 3
Bit 3
Bit 3
R
3
0
1
1
0
0
0
0
ELS0A
ELS1A
TRIM2
Bit 10
Bit 10
Bit 10
U = Unaffected
Bit 2
Bit 2
Bit 2
Bit 2
R
Input/Output (I/O) Section
2
0
1
1
0
0
0
0
ECGON
TRIM1
TOV0
TOV1
Bit 1
Bit 9
Bit 1
Bit 9
Bit 1
Bit 9
Bit 1
1
0
1
1
0
0
0
0
CH0MAX
CH1MAX
ECGST
TRIM0
Bit 0
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
0
1
1
0
0
0
0
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