MCHC908QY1CDWE Freescale Semiconductor, MCHC908QY1CDWE Datasheet - Page 30

• Manufacturer Part Number: MCHC908QY1CDWE
• Description: IC MCU 1.5K FLASH 16-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908QY1CDWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 1.5KB (1.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Processor Series: HC08QY
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

Memory
30
$003C
$003D
$FE00
$FE01
$FE02
$FE03
$FE04
$FE05
$FE06
$FE07
$0039
$003B
$003E
$003F
Addr.
↓
SIM Reset Status Register
Interrupt Status Register 1
Interrupt Status Register 2
Interrupt Status Register 3
ADC Input Clock Register
ADC Status and Control
Break Status Register
Register Name
ADC Data Register
Break Flag Control
Register (ADSCR)
Register (BRKAR)
Register (BFCR)
Unimplemented
Unimplemented
Break Auxiliary
See page 137.
See page 117.
See page 137.
See page 138.
See page 45.
See page 47.
See page 47.
See page 77.
See page 77.
See page 77.
(ADICLK)
Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 5)
(SRSR)
(INT1)
(INT2)
(INT3)
(ADR)
(BSR)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
POR:
MC68HC908QY/QT Family Data Sheet, Rev. 6
1. Writing a 0 clears SBSW.
COCO
ADIV2
BCFE
Bit 7
POR
Bit 7
IF14
R
R
R
R
R
R
0
0
1
0
0
0
0
0
0
0
0
= Unimplemented
ADIV1
AIEN
Bit 6
PIN
IF5
R
R
R
R
R
R
6
0
0
0
0
0
0
0
0
0
0
ADCO
ADIV0
COP
Bit 5
IF4
R
R
R
R
R
R
5
0
0
0
0
0
0
0
0
0
0
Indeterminate after reset
ILOP
CH4
Bit 4
IF3
R
R
R
R
R
R
R
4
1
0
0
0
0
0
0
0
0
0
0
= Reserved
ILAD
CH3
Bit 3
R
R
R
R
R
R
3
1
0
0
0
0
0
0
0
0
0
0
0
MODRST
U = Unaffected
CH2
Bit 2
IF1
R
R
R
R
R
R
2
1
0
0
0
0
0
0
0
0
0
0
Freescale Semiconductor
See note 1
SBSW
CH1
Bit 1
LVI
R
R
R
R
R
1
1
0
0
0
0
0
0
0
0
0
0
0
0
BDCOP
Bit 0
CH0
Bit 0
IF15
R
R
R
R
R
R
1
0
0
0
0
0
0
0
0
0
0