R5F212B7SNFP#U0 Renesas Electronics America, R5F212B7SNFP#U0 Datasheet
R5F212B7SNFP#U0
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R5F212B7SNFP#U0 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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R8C/2A Group, 16 R8C/2B Group Hardware Manual RENESAS MCU R8C FAMILY / R8C/2x SERIES All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change ...
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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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How to Use This Manual 1. Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU intended for users designing application systems incorporating ...
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Notation of Numbers and Symbols The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below. (1) Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in ...
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Register Notation The symbols and terms used in register diagrams are described below. XXX Register Bit Symbol XXX0 XXX1 XXX4 XXX5 XXX6 XXX7 *1 Blank: Set ...
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List of Abbreviations and Acronyms Abbreviation ACIA bps CRC DMA DMAC GSM Hi-Z IEBus I/O IrDA LSB MSB NC PLL PWM SFR SIM UART VCO All trademarks and registered trademarks are the property of their respective owners. Asynchronous Communication ...
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SFR Page Reference ........................................................................................................................... Overview ......................................................................................................................................... 1 1.1 Features ..................................................................................................................................................... 1 1.1.1 Applications .......................................................................................................................................... 1 1.1.2 Specifications ........................................................................................................................................ 2 1.2 Product List ............................................................................................................................................... 6 1.3 Block Diagram ....................................................................................................................................... 10 1.4 Pin Assignment ........................................................................................................................................ 11 1.5 Pin ...
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Voltage Detection Circuit .............................................................................................................. 42 6.1 VCC Input Voltage .................................................................................................................................. 49 6.1.1 Monitoring Vdet0 ............................................................................................................................... 49 6.1.2 Monitoring Vdet1 ............................................................................................................................... 49 6.1.3 Monitoring Vdet2 ............................................................................................................................... 49 6.2 Voltage Monitor 0 Reset ......................................................................................................................... 50 6.3 Voltage Monitor 1 Interrupt and ...
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Protection .................................................................................................................................... 121 12. Interrupts ..................................................................................................................................... 122 12.1 Interrupt Overview ................................................................................................................................ 122 12.1.1 Types of Interrupts ............................................................................................................................ 122 12.1.2 Software Interrupts ........................................................................................................................... 123 12.1.3 Special Interrupts .............................................................................................................................. 124 12.1.4 Peripheral Function Interrupt ............................................................................................................ 124 12.1.5 Interrupts and Interrupt Vectors ...
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PWM2 Mode ..................................................................................................................................... 229 14.3.8 Timer RC Interrupt ........................................................................................................................... 235 14.3.9 Notes on Timer RC ........................................................................................................................... 236 14.4 Timer RD ............................................................................................................................................... 237 14.4.1 Count Sources ................................................................................................................................... 242 14.4.2 Buffer Operation ............................................................................................................................... 243 14.4.3 Synchronous Operation ..................................................................................................................... 245 14.4.4 Pulse ...
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Clock Synchronous Serial Mode ...................................................................................................... 447 16.3.5 Examples of Register Setting ............................................................................................................ 450 16.3.6 Noise Canceller ................................................................................................................................. 454 16.3.7 Bit Synchronization Circuit .............................................................................................................. 455 2 16.3.8 Notes bus Interface ................................................................................................................ 456 17. Hardware LIN .............................................................................................................................. 457 ...
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Electrical Characteristics ............................................................................................................ 520 22. Usage Notes ............................................................................................................................... 545 22.1 Notes on Clock Generation Circuit ....................................................................................................... 545 22.1.1 Stop Mode ......................................................................................................................................... 545 22.1.2 Wait Mode ........................................................................................................................................ 545 22.1.3 Oscillation Stop Detection Function ................................................................................................. 545 22.1.4 Oscillation Circuit Constants ............................................................................................................ ...
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SFR Page Reference Address Register 0000h 0001h 0002h 0003h 0004h Processor Mode Register 0 0005h Processor Mode Register 1 0006h System Clock Control Register 0 0007h System Clock Control Register 1 0008h Module Standby Control Register 0009h 000Ah Protect Register ...
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Address Register 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h UART0 Transmit/Receive Mode Register 00A1h ...
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Address Register 0100h Timer RA Control Register 0101h Timer RA I/O Control Register 0102h Timer RA Mode Register 0103h Timer RA Prescaler Register 0104h Timer RA Register 0105h LIN Control Register 2 0106h LIN Control Register 0107h LIN Status Register ...
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Address Register 0160h UART2 Transmit/Receive Mode Register 0161h UART2 Bit Rate Register 0162h UART2 Transmit Buffer Register 0163h 0164h UART2 Transmit/Receive Control Register 0 0165h UART2 Transmit/Receive Control Register 1 0166h UART2 Receive Buffer Register 0167h 0168h 0169h 016Ah 016Bh ...
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Address Register 01E0h 01E1h 01E2h 01E3h 01E4h 01E5h 01E6h 01E7h 01E8h 01E9h 01EAh 01EBh 01ECh 01EDh 01EEh 01EFh 01F0h 01F1h 01F2h 01F3h 01F4h 01F5h 01F6h 01F7h 01F8h 01F9h 01FAh 01FBh 01FCh 01FDh 01FEh 01FFh 0200h 0201h 0202h 0203h 0204h 0205h ...
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Address Register 0260h 0261h 0262h 0263h 0264h 0265h 0266h 0267h 0268h 0269h 026Ah 026Bh 026Ch 026Dh 026Eh 026Fh 0270h 0271h 0272h 0273h 0274h 0275h 0276h 0277h 0278h 0279h 027Ah 027Bh 027Ch 027Dh 027Eh 027Fh 0280h 0281h 0282h 0283h 0284h 0285h ...
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Address Register 02E0h 02E1h 02E2h 02E3h 02E4h Port P8 Direction Register 02E5h 02E6h Port P8 Register 02E7h 02E8h 02E9h 02EAh 02EBh 02ECh 02EDh 02EEh 02EFh 02F0h 02F1h 02F2h 02F3h 02F4h 02F5h 02F6h 02F7h 02F8h 02F9h 02FAh 02FBh 02FCh Pull-Up Control ...
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R8C/2A Group, R8C/2B Group RENESAS MCU 1. Overview 1.1 Features The R8C/2A Group and R8C/2B Group of single-chip MCUs incorporates the R8C/Tiny Series CPU core, employing sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, ...
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R8C/2A Group, R8C/2B Group 1.1.2 Specifications Tables 1.1 and 1.2 outlines the Specifications for R8C/2A Group and Tables 1.3 and 1.4 outlines the Specifications for R8C/2B Group. Table 1.1 Specifications for R8C/2A Group (1) Item Function CPU Central processing unit ...
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R8C/2A Group, R8C/2B Group Table 1.2 Specifications for R8C/2A Group (2) Item Function Serial UART0, UART1, Interface UART2 Clock Synchronous Serial I/O with Chip Select (SSU bus LIN Module A/D Converter D/A Converter Flash Memory Operating ...
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R8C/2A Group, R8C/2B Group Table 1.3 Specifications for R8C/2B Group (1) Item Function CPU Central processing unit Memory ROM, RAM Power Supply Voltage detection Voltage circuit Detection I/O Ports Programmable I/O ports Clock Clock generation circuits Interrupts Watchdog Timer Timer ...
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R8C/2A Group, R8C/2B Group Table 1.4 Specifications for R8C/2B Group (2) Item Function Serial UART0, UART1, Interface UART2 Clock Synchronous Serial I/O with Chip Select (SSU bus LIN Module A/D Converter D/A Converter Flash Memory Operating ...
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R8C/2A Group, R8C/2B Group 1.2 Product List Table 1.5 lists Product List for R8C/2A Group, Figure 1.1 shows a Part Number, Memory Size, and Package of R8C/2A Group, Table 1.6 lists Product List for R8C/2B Group, and Figure 1.2 shows ...
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R8C/2A Group, R8C/2B Group Part No XXX FP NOTE: 1: Please contact Renesas Technology sales offices for the Y version. Figure 1.1 Part Number, Memory Size, and Package of R8C/2A Group Rev.2.00 ...
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R8C/2A Group, R8C/2B Group Table 1.6 Product List for R8C/2B Group Part No. Program ROM R5F212B7SNFP 48 Kbytes R5F212B7SNFA 48 Kbytes R5F212B7SNLG 48 Kbytes R5F212B8SNFP 64 Kbytes R5F212B8SNFA 64 Kbytes R5F212B8SNLG 64 Kbytes R5F212BASNFP 96 Kbytes R5F212BASNFA 96 Kbytes R5F212BASNLG ...
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R8C/2A Group, R8C/2B Group Part No XXX FP NOTE: 1: Please contact Renesas Technology sales offices for the Y version. Figure 1.2 Part Number, Memory Size, and Package of R8C/2B Group Rev.2.00 ...
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R8C/2A Group, R8C/2B Group 1.3 Block Diagram Figure 1.3 shows a Block Diagram. I/O ports Peripheral functions Timers Timer RA (8 bits × 1) Timer RB (8 bits × 1) Timer RC (16 bits × 1) Timer RD (16 bits ...
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R8C/2A Group, R8C/2B Group 1.4 Pin Assignment Figure 1.4 shows 64-pin LQFP Package Pin Assignment (Top View). Figure 1.5 shows 64-pin FLGA Package Pin Assignment (Top Perspective View). Tables 1.7 and 1.8 outlines the Pin Name Information by Pin Number. ...
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R8C/2A Group, R8C/2B Group P3_3/SSI P0_1/AN6 7 P3_4/SDA/ P0_0/AN7 SCS 6 P5_3/ MODE TRCIOC 5 P4_4/XCOUT P2_5/ TRDIOB1 4 P5_4/ VCC/AVCC TRCIOD 3 VSS/AVSS VSS/AVSS 2 P5_1/TRCIOA/ P4_6/XIN TRCTRG 1 P2_7/ P2_6/ TRDIOD1 TRDIOC1 A B NOTES: ...
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R8C/2A Group, R8C/2B Group Table 1.7 Pin Name Information by Pin Number (1) Pin Control Pin Port Number 1 P3_3 2 P3_4 3 MODE 4 XCIN P4_3 5 XCOUT P4_4 6 RESET 7 XOUT P4_7 8 VSS/AVSS 9 XIN P4_6 ...
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R8C/2A Group, R8C/2B Group Table 1.8 Pin Name Information by Pin Number (2) Pin Control Pin Port Number 46 P1_3 47 P1_2 48 P1_1 49 P1_0 50 P0_0 51 P0_1 52 P0_2 53 P0_3 54 P0_4 55 P6_2 56 P6_1 ...
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R8C/2A Group, R8C/2B Group 1.5 Pin Functions Tables 1.9 and 1.10 list Pin Functions. Table 1.9 Pin Functions (1) Item Pin Name Power supply input VCC, VSS Analog power AVCC, AVSS supply input Reset input RESET MODE MODE XIN clock ...
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R8C/2A Group, R8C/2B Group Table 1.10 Pin Functions (2) Item Pin Name A/D converter AN0 to AN11 D/A converter DA0 to DA1 I/O port P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_3 to P4_5, P5_0 ...
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R8C/2A Group, R8C/2B Group 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two sets of register bank. b31 ...
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R8C/2A Group, R8C/2B Group 2.1 Data Registers (R0, R1, R2, and R3 16-bit register for transfer, arithmetic, and logic operations. The same applies R3. R0 can be split into high-order bits (R0H) and low-order ...
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R8C/2A Group, R8C/2B Group 2.8.7 Interrupt Enable Flag (I) The I flag enables maskable interrupts. Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag ...
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R8C/2A Group, R8C/2B Group 3. Memory 3.1 R8C/2A Group Figure 3 Memory Map of R8C/2A Group. The R8C/2A group has 1 Mbyte of address space from addresses 00000h to FFFFFh. The internal ROM is allocated lower addresses, beginning ...
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R8C/2A Group, R8C/2B Group 3.2 R8C/2B Group Figure 3 Memory Map of R8C/2B Group. The R8C/2B group has 1 Mbyte of address space from addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning ...
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R8C/2A Group, R8C/2B Group 4. Special Function Registers (SFRs) An SFR (special function register control register for a peripheral function. Tables 4.1 to 4.12 list the special function registers. Table 4.1 SFR Information (1) Address 0000h 0001h 0002h ...
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R8C/2A Group, R8C/2B Group Table 4.2 SFR Information (2) Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h Timer RC Interrupt Control Register 0048h Timer RD0 Interrupt Control Register 0049h Timer RD1 Interrupt Control Register 004Ah Timer RE Interrupt Control ...
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R8C/2A Group, R8C/2B Group Table 4.3 SFR Information (3) Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh ...
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R8C/2A Group, R8C/2B Group Table 4.4 SFR Information (4) Address 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h 00D5h 00D6h 00D7h 00D8h D/A Register 0 00D9h 00DAh ...
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R8C/2A Group, R8C/2B Group Table 4.5 SFR Information (5) Address 0100h Timer RA Control Register 0101h Timer RA I/O Control Register 0102h Timer RA Mode Register 0103h Timer RA Prescaler Register 0104h Timer RA Register 0105h LIN Control Register 2 ...
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R8C/2A Group, R8C/2B Group Table 4.6 SFR Information (6) Address 0140h Timer RD Control Register 0 0141h Timer RD I/O Control Register A0 0142h Timer RD I/O Control Register C0 0143h Timer RD Status Register 0 0144h Timer RD Interrupt ...
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R8C/2A Group, R8C/2B Group Table 4.7 SFR Information (7) Address 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh ...
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R8C/2A Group, R8C/2B Group Table 4.8 SFR Information (8) Address 01C0h 01C1h 01C2h 01C3h 01C4h 01C5h 01C6h 01C7h 01C8h 01C9h 01CAh 01CBh 01CCh 01CDh 01CEh 01CFh 01D0h 01D1h 01D2h 01D3h 01D4h 01D5h 01D6h 01D7h 01D8h 01D9h 01DAh 01DBh 01DCh 01DDh ...
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R8C/2A Group, R8C/2B Group Table 4.9 SFR Information (9) Address 0200h 0201h 0202h 0203h 0204h 0205h 0206h 0207h 0208h 0209h 020Ah 020Bh 020Ch 020Dh 020Eh 020Fh 0210h 0211h 0212h 0213h 0214h 0215h 0216h 0217h 0218h 0219h 021Ah 021Bh 021Ch 021Dh ...
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R8C/2A Group, R8C/2B Group Table 4.10 SFR Information (10) Address 0240h 0241h 0242h 0243h 0244h 0245h 0246h 0247h 0248h 0249h 024Ah 024Bh 024Ch 024Dh 024Eh 024Fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025Ah 025Bh 025Ch 025Dh ...
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R8C/2A Group, R8C/2B Group Table 4.11 SFR Information (11) Address 0280h 0281h 0282h 0283h 0284h 0285h 0286h 0287h 0288h 0289h 028Ah 028Bh 028Ch 028Dh 028Eh 028Fh 0290h Timer RF Register 0291h 0292h 0293h 0294h 0295h 0296h 0297h 0298h 0299h 029Ah ...
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R8C/2A Group, R8C/2B Group Table 4.12 SFR Information (12) Address 02C0h A/D Register 0 02C1h 02C2h 02C3h 02C4h 02C5h 02C6h 02C7h 02C8h 02C9h 02CAh 02CBh 02CCh 02CDh 02CEh 02CFh 02D0h 02D1h 02D2h 02D3h 02D4h A/D Control Register 2 02D5h 02D6h ...
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R8C/2A Group, R8C/2B Group 5. Resets The following resets are implemented: hardware reset, power-on reset, voltage monitor 0 reset, voltage monitor 1 reset, voltage monitor 2 reset, watchdog timer reset, and software reset. Table 5.1 lists the Reset Names and ...
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R8C/2A Group, R8C/2B Group Table 5.2 shows the Pin Functions while RESET Pin Level is “L”, Figure 5.2 shows the CPU Register Status after Reset, Figure 5.3 shows the Reset Sequence, and Figure 5.4 shows the OFS Register. Table 5.2 ...
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R8C/2A Group, R8C/2B Group fOCO-S RESET pin 10 cycles or more are needed fOCO-S clock × 32 cycles Internal reset signal Start time of flash memory (CPU clock × 14 cycles) CPU clock Address (internal address signal) NOTES: 1. Hardware ...
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R8C/2A Group, R8C/2B Group 5.1 Hardware Reset A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the supply voltage meets the recommended operating conditions, pins, CPU, and SFRs are all ...
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R8C/2A Group, R8C/2B Group VCC RESET Figure 5.5 Example of Hardware Reset Circuit and Operation RESET Figure 5.6 Example of Hardware Reset Circuit (Usage Example of External Supply Voltage Detection Circuit) and Operation Rev.2.00 Nov 26, 2007 Page 38 of ...
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R8C/2A Group, R8C/2B Group 5.2 Power-On Reset Function When the RESET pin is connected to the VCC pin via a pull-up resistor, and the VCC pin voltage level rises while the rise gradient is trth or more, the power-on reset ...
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R8C/2A Group, R8C/2B Group 5.3 Voltage Monitor 0 Reset A reset is applied using the on-chip voltage detection 0 circuit. The voltage detection 0 circuit monitors the input voltage to the VCC pin. The voltage to monitor is Vdet0. When ...
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R8C/2A Group, R8C/2B Group 5.6 Watchdog Timer Reset When the PM12 bit in the PM1 register is set to 1 (reset when watchdog timer underflows), the MCU resets its pins, CPU, and SFR if the watchdog timer underflows. Then the ...
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R8C/2A Group, R8C/2B Group 6. Voltage Detection Circuit The voltage detection circuit monitors the input voltage to the VCC pin. This circuit can be used to monitor the VCC input voltage by a program. Alternately, voltage monitor 0 reset, voltage ...
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R8C/2A Group, R8C/2B Group VCC Internal reference voltage Figure 6.1 Block Diagram of Voltage Detection Circuit Voltage detection 0 circuit VCA25 VCC + Internal - reference voltage Voltage detection 0 signal is held “H” when VCA25 bit is set to ...
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R8C/2A Group, R8C/2B Group Voltage detection 1 circuit fOCO-S VCA26 VCC + Noise filter Voltage Internal - detection reference 1 signal (Filter width: 200 ns) voltage Voltage detection 1 signal is held “H” when VCA26 bit is set to 0 ...
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R8C/2A Group, R8C/2B Group Voltage Detection Register Symbol VCA1 Bit Symbol — (b2-b0) VCA13 — (b7-b4) NOTES: 1. The VCA13 bit is enabled w ...
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R8C/2A Group, R8C/2B Group Voltage Monitor 0 Circuit Control Register Symbol VW0C Bit Symbol VW0C0 VW0C1 VW0C2 — (b3) VW0F0 VW0F1 VW0C6 VW0C7 NOTES: 1. Set the PRC3 bit in the ...
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R8C/2A Group, R8C/2B Group Voltage Monitor 1 Circuit Control Register Symbol VW1C Bit Symbol VW1C0 VW1C1 VW1C2 VW1C3 VW1F0 VW1F1 VW1C6 VW1C7 NOTES: 1. Set the PRC3 bit in the PRCR register ...
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R8C/2A Group, R8C/2B Group Voltage Monitor 2 Circuit Control Register Symbol VW2C Bit Symbol VW2C0 VW2C1 VW2C2 VW2C3 VW2F0 VW2F1 VW2C6 VW2C7 NOTES: 1. Set the PRC3 bit in the PRCR register ...
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R8C/2A Group, R8C/2B Group 6.1 VCC Input Voltage 6.1.1 Monitoring Vdet0 Vdet0 cannot be monitored. 6.1.2 Monitoring Vdet1 Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled). After td(E-A) has elapsed (refer to 21. ...
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R8C/2A Group, R8C/2B Group 6.2 Voltage Monitor 0 Reset Table 6.2 lists the Procedure for Setting Bits Associated with Voltage Monitor Reset and Figure 6.9 shows an Example of Voltage Monitor 0 Reset Operation. To use the voltage monitor 0 ...
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R8C/2A Group, R8C/2B Group 6.3 Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset Table 6.3 lists the Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt and Reset. Figure 6.10 shows an Example of Voltage Monitor 1 Interrupt ...
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R8C/2A Group, R8C/2B Group Vdet1 2.2 V VW1C3 bit VW1C2 bit When the VW1C1 bit is set to 0 (digital filter enabled) Voltage monitor 1 interrupt request (VW1C6 = 0) Internal reset signal (VW1C6 = 1) VW1C2 bit When the ...
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R8C/2A Group, R8C/2B Group 6.4 Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Table 6.4 lists the Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt and Reset. Figure 6.11 shows an Example of Voltage Monitor 2 Interrupt ...
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R8C/2A Group, R8C/2B Group Vdet2 2.2 V VCA13 bit VW2C2 bit When the VW2C1 bit is set to 0 (digital filter enabled) Voltage monitor 2 interrupt request (VW2C6 = 0) Internal reset signal (VW2C6 = 1) VW2C2 bit When the ...
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R8C/2A Group, R8C/2B Group 7. Programmable I/O Ports There are 55 programmable Input/Output ports (I/O ports P3, P4_3 to P4_5, P5_0 to P5_4, P6, and P8_0 to P8_6. Also, P4_6 and P4_7 can be used as input-only ports ...
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R8C/2A Group, R8C/2B Group 7.2 Effect on Peripheral Functions Programmable I/O ports function as I/O ports for peripheral functions (Refer to Table 1.7 Pin Name Information by Pin Number (1) and Table 1.8 Pin Name Information by Pin Number (2)). ...
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R8C/2A Group, R8C/2B Group P0_0 to P0_4 Direction Data bus Port latch P0_5 Direction Output from individual peripheral function Data bus Port latch Input to individual peripheral function P0_6 and P0_7 Direction Data bus Port latch NOTE: 1. Ensure the ...
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R8C/2A Group, R8C/2B Group P1_0 to P1_3 Direction register Output from individual peripheral function Data bus Port latch Input to individual peripheral function P1_4 Direction register Output from individual peripheral function Data bus Port latch P1_5 and P1_7 Direction register ...
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R8C/2A Group, R8C/2B Group P1_6 Direction register Output from individual peripheral function Data bus Port latch Input to individual peripheral function P2 Direction register Output from individual peripheral function Data bus Port latch Input to individual peripheral function P3_0 and ...
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R8C/2A Group, R8C/2B Group P3_2 and P3_6 Data bus Input to INT1 and INT2 P3_3, P3_4, P3_5, and P3_7 Output from individual peripheral function Data bus Input to individual peripheral function NOTE: 1. Ensure the input voltage to each port ...
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R8C/2A Group, R8C/2B Group P4_3/XCIN Data bus P4_4/XCOUT Data bus P4_5 Data bus NOTES: 1. Ensure the input voltage to each port does not exceed VCC. 2. When CM10 = 1 or CM04 = 0, the clocked inverter is cut ...
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R8C/2A Group, R8C/2B Group P4_6/XIN P4_7/XOUT P5_0 Data bus Input to individual peripheral function NOTES: 1. Ensure the input voltage to each port does not exceed VCC. 2. When CM05 = 1, CM10 = 1, or CM13 = 0, the ...
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R8C/2A Group, R8C/2B Group P5_1 to P5_4 Output from individual peripheral function Data bus Input to individual peripheral function P6_0 Output from individual peripheral function Data bus NOTE: 1. Ensure the input voltage to each port does not exceed VCC. ...
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R8C/2A Group, R8C/2B Group P6_1 and P6_2 Data bus P6_3 Direction Output from individual peripheral function Data bus Port latch P6_4 Data bus Input to individual peripheral function NOTE: 1. Ensure the input voltage to each port does not exceed ...
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R8C/2A Group, R8C/2B Group P6_5 Direction Output from individual peripheral function Data bus Port latch Input to individual peripheral function P6_6 Output from individual peripheral function Data bus Data bus P6_7 Data bus Input to individual peripheral function NOTE: 1. ...
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R8C/2A Group, R8C/2B Group P8_0 to P8_2, P8_4, and P8_5 Direction register Output from individual peripheral function Data bus Port latch P8_3 Direction register Output from individual peripheral function Data bus Port latch Input to individual peripheral function P8_6 Data ...
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R8C/2A Group, R8C/2B Group MODE MODE signal input RESET RESET signal input NOTE: 1. Ensure the input voltage to each port does not exceed VCC. Figure 7.11 Configuration of I/O Pins Rev.2.00 Nov 26, 2007 Page 67 of 580 REJ09B0324-0200 ...
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R8C/2A Group, R8C/2B Group Port Pi Direction Register ( Symbol PD0 (1) PD1 PD2 PD3 (2) PD4 PD5 (3) PD6 (4) PD8 Bit Symbol PDi_0 PDi_1 PDi_2 ...
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R8C/2A Group, R8C/2B Group Port Pi Register ( Symbol ( (3) Bit Symbol Pi_0 Pi_1 Pi_2 Pi_3 Pi_4 ...
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R8C/2A Group, R8C/2B Group Port P2 Drive Capacity Control Register Symbol P2DRR Bit Symbol P2DRR0 P2DRR1 P2DRR2 P2DRR3 P2DRR4 P2DRR5 P2DRR6 P2DRR7 NOTE: 1. Both “H” and “L” output are set to ...
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R8C/2A Group, R8C/2B Group Pull-Up Control Register Symbol PUR0 Bit Symbol PU00 PU01 PU02 PU03 PU04 PU05 PU06 PU07 NOTE: 1. When this bit is set to 1 (pulled up), the ...
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R8C/2A Group, R8C/2B Group 7.4 Port settings Tables 7.4 to 7.65 list the port settings. Table 7.4 Port P0_0/AN7 Register PD0 Bit PD0_0 CH2 0 X Setting 1 X Value NOTE: 1. Pulled up ...
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R8C/2A Group, R8C/2B Group Table 7.9 Port P0_5/AN2/CLK1 Register PD0 ADCON0 Bit PD0_5 CH2 CH1 CH0 ADGSEL1 ADGSEL0 U1PINSEL SMD2 SMD1 SMD0 CKDIR CLK11PSEL CLK10PSEL Setting Value ...
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R8C/2A Group, R8C/2B Group Table 7.12 Port P1_0/KI0/AN8 Register PD1 KIEN Bit PD1_0 KI0EN Setting Value NOTE: 1. Pulled up by setting the PU02 bit in the PUR0 ...
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R8C/2A Group, R8C/2B Group Table 7.17 Port P1_5/RXD0/(TRAIO)/(INT1) Register PD1 TRAIOC Bit PD1_5 TIOSEL Setting X Value NOTE: 1. Pulled ...
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R8C/2A Group, R8C/2B Group Table 7.20 Port P2_0/TRDIOA0/TRDCLK Register PD2 TRDOER1 Bit PD2_0 EA0 CMD1 CMD0 STCLK PWM3 Setting 0 X Value NOTES: 1. Pulled up ...
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R8C/2A Group, R8C/2B Group Table 7.23 Port P2_3/TRDIOD0 Register PD2 TRDOER1 Bit PD2_3 ED0 CMD1 Setting Value NOTES: 1. Pulled up by ...
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R8C/2A Group, R8C/2B Group Table 7.26 Port P2_6/TRDIOC1 Register PD2 TRDOER1 Bit PD2_6 EC1 CMD1 Setting Value NOTES: 1. Pulled up by ...
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R8C/2A Group, R8C/2B Group Table 7.28 Port P3_0/TRAO Register PD3 Bit PD3_0 0 Setting 1 Value NOTE: 1. Pulled up by setting the PU06 bit in the PUR0 register to 1. Table 7.29 Port P3_1/TRBO ...
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R8C/2A Group, R8C/2B Group Table 7.32 Port P3_4/SDA/SCS Register PD3 Bit PD3_4 CSS1 Setting Value NOTES: 1. Pulled up by setting ...
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R8C/2A Group, R8C/2B Group Table 7.36 VREF Register ADCON1 Bit VCUT 0 Setting Value 1 Table 7.37 Port P4_3/XCIN Register PD4 CM0 Bit PD4_3 CM04 Setting X 1 Value ...
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R8C/2A Group, R8C/2B Group Table 7.40 Port P4_6/XIN Register CM1 Bit CM13 CM10 0 1 Setting 1 Value Table 7.41 Port P4_7/XOUT Register CM1 Bit CM13 CM10 0 1 Setting 1 Value 1 1 ...
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R8C/2A Group, R8C/2B Group Table 7.42 Port P5_0/TRCCLK Register PD5 Bit PD5_0 0 Setting 1 Value 0 NOTE: 1. Pulled up by setting the PU12 bit in the PUR1 register to 1. Table 7.43 Port P5_1/TRCIOA/TRCTRG Register PD5 Bit PD5_1 ...
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R8C/2A Group, R8C/2B Group Table 7.47 Port P5_3/TRCIOC Register PD5 Bit PD5_3 0 1 Setting Value NOTE: 1. Pulled up by setting the PU12 bit in the PUR1 register to 1. Table 7.48 TRCIOC ...
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R8C/2A Group, R8C/2B Group Table 7.51 Port P6_0/TREO Register PD6 Bit PD6_0 0 Setting 1 Value NOTE: 1. Pulled up by setting the PU14 bit in the PUR1 register to 1. Table 7.52 Port P6_1 ...
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R8C/2A Group, R8C/2B Group Table 7.56 Port P6_5/(CLK1)/CLK2 Register PD6 PMR Bit PD6_5 U1PINSEL Setting 1 0 Value NOTE: 1. Pulled up ...
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R8C/2A Group, R8C/2B Group Table 7.59 Port P8_0/TRFO00 Register PD8 Bit PD8_0 TRFOUT0 0 Setting 1 Value NOTE: 1. Pulled up by setting the PU22 bit in the PUR2 register to 1. Table 7.60 ...
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R8C/2A Group, R8C/2B Group Table 7.64 Port P8_5/TRFO12 Register PD8 Bit PD8_5 TRFOUT5 0 Setting 1 Value NOTE: 1. Pulled up by setting the PU23 bit in the PUR2 register to 1. Table 7.65 ...
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R8C/2A Group, R8C/2B Group 7.5 Unassigned Pin Handling Table 7.66 lists Unassigned Pin Handling. Table 7.66 Unassigned Pin Handling Pin Name Ports P0 to P3, P4_3 to P4_5, P5_0 to P5_4, P6, P8_0 to P8_6 Ports P4_6, P4_7 VREF (3) ...
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R8C/2A Group, R8C/2B Group 8. Processor Mode 8.1 Processor Modes Single-chip mode can be selected as the processor mode. Table 8.1 lists Features of Processor Mode. Figure 8.1 shows the PM0 Register and Figure 8.2 shows the PM1 Register. Table ...
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R8C/2A Group, R8C/2B Group 9. Bus The bus cycles differ when accessing ROM/RAM, and when accessing SFR. Table 9.1 lists Bus Cycles by Access Space of the R8C/2A Group and Table 9.2 lists Bus Cycles by Access Space of the ...
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R8C/2A Group, R8C/2B Group Table 9.4 Access Units and Bus Operations of SFR (address 0200h to 02FFh) Area Even address CPU clock Byte access Address Data Odd address CPU clock Byte access Address Data Even address CPU clock Word access ...
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R8C/2A Group, R8C/2B Group 10. Clock Generation Circuit The clock generation circuit has: • XIN clock oscillation circuit • XCIN clock oscillation circuit • Low-speed on-chip oscillator • High-speed on-chip oscillator Table 10.1 lists Specifications of Clock Generation Circuit. Figure ...
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R8C/2A Group, R8C/2B Group XCOUT XCIN CM04 S Q CM10 = 1 (stop mode) R RESET Power-on reset Software reset Interrupt request WAIT instruction CM13 XIN XOUT CM13 CM05 CM02, CM04, CM05, CM06, CM07: Bits in CM0 ...
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R8C/2A Group, R8C/2B Group fC4 fC32 fOCO40M fOCO128 fOCO fOCO-F Watchdog fOCO-S timer INT0 Timer RA Timer f32 CPU clock Figure 10.2 Peripheral Function Clock Rev.2.00 Nov 26, 2007 Page 95 of 580 REJ09B0324-0200 Timer ...
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R8C/2A Group, R8C/2B Group System Clock Control Register Symbol CM0 Bit Symbol — (b1-b0) CM02 CM03 CM04 CM05 CM06 CM07 NOTES: 1. Set the PRC0 bit in the PRCR ...
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R8C/2A Group, R8C/2B Group System Clock Control Register Symbol CM1 Bit Symbol CM10 CM11 CM12 CM13 CM14 CM15 CM16 CM17 NOTES: 1. Set the PRC0 bit in the PRCR register to ...
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R8C/2A Group, R8C/2B Group Oscillation Stop Detection Register Symbol OCD Bit Symbol OCD0 OCD1 OCD2 OCD3 — (b7-b4) NOTES: 1. Set the PRC0 bit in the PRCR register ...
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R8C/2A Group, R8C/2B Group High-Speed On-Chip Oscillator Control Register Symbol FRA0 Bit Symbol FRA00 FRA01 — (b7-b2) NOTES: Set the PRC0 bit in the PRCR ...
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R8C/2A Group, R8C/2B Group High-Speed On-Chip Oscillator Control Register Symbol FRA2 Bit Symbol FRA20 FRA21 FRA22 — (b7-b3) NOTE: 1. Set the PRC0 bit in the ...
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R8C/2A Group, R8C/2B Group Clock Prescaler Reset Flag Symbol CPSRF Bit Symbol — (b6-b0) CPSR NOTE: 1. Only w rite 1 to this bit w ...
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R8C/2A Group, R8C/2B Group Handling procedure of internal power low consumption enabled by VCA20 bit Enter low-speed clock mode or low-speed Step (1) on-chip oscillator mode Stop XIN clock and high-speed on-chip Step (2) oscillator clock VCA20 ← 1 (internal ...
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R8C/2A Group, R8C/2B Group The clocks generated by the clock generation circuits are described below. 10.1 XIN Clock This clock is supplied by the XIN clock oscillation circuit. This clock is used as the clock source for the CPU and ...
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R8C/2A Group, R8C/2B Group 10.2 On-Chip Oscillator Clocks These clocks are supplied by the on-chip oscillators (high-speed on-chip oscillator and a low-speed on-chip oscillator). The on-chip oscillator clock is selected by the FRA01 bit in the FRA0 register. 10.2.1 Low-Speed ...
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R8C/2A Group, R8C/2B Group 10.3 XCIN Clock This clock is supplied by the XCIN clock oscillation circuit. This clock is used as the clock source for the CPU clock, timer RA, and timer RE. The XCIN clock oscillation circuit is ...
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R8C/2A Group, R8C/2B Group 10.4 CPU Clock and Peripheral Function Clock There are a CPU clock to operate the CPU and a peripheral function clock to operate the peripheral functions. Refer to Figure 10.1 Clock Generation Circuit. 10.4.1 System Clock ...
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R8C/2A Group, R8C/2B Group 10.4.9 fC4 and fC32 The clock fC4 and fC32 are used for timer RA and timer RE. Use fC4 and fC32 while the XCIN clock oscillation stabilizes. Rev.2.00 Nov 26, 2007 Page 107 of 580 REJ09B0324-0200 ...
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R8C/2A Group, R8C/2B Group 10.5 Power Control There are three power control modes. All modes other than wait mode and stop mode are referred to as standard operating mode. 10.5.1 Standard Operating Mode Standard operating mode is further separated into ...
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R8C/2A Group, R8C/2B Group 10.5.1.1 High-Speed Clock Mode The XIN clock divided by 1 (no division provides the CPU clock. Set the CM06 bit to 1 (divide- by-8 mode) when transiting to high-speed on-chip oscillator ...
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R8C/2A Group, R8C/2B Group 10.5.2 Wait Mode Since the CPU clock stops in wait mode, the CPU, which operates using the CPU clock, and the watchdog timer, when count source protection mode is disabled, stop. The XIN clock, XCIN clock, ...
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R8C/2A Group, R8C/2B Group 10.5.2.4 Exiting Wait Mode The MCU exits wait mode by a reset or a peripheral function interrupt. The peripheral function interrupts are affected by the CM02 bit. When the CM02 bit is set to 0 (peripheral ...
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R8C/2A Group, R8C/2B Group Figure 10.13 shows the Time from Wait Mode to Interrupt Routine Execution. When using a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT instruction. (1) Set the interrupt priority ...
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R8C/2A Group, R8C/2B Group 10.5.2.5 Reducing Internal Power Consumption Internal power consumption can be reduced by using low-speed clock mode or low-speed on-chip oscillator mode. Figure 10.14 shows the Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit. When ...
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R8C/2A Group, R8C/2B Group 10.5.3 Stop Mode Since the oscillator circuits stop in stop mode, the CPU clock and peripheral function clock stop and the CPU and peripheral functions that use these clocks stop operating. The least power required to ...
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R8C/2A Group, R8C/2B Group 10.5.3.3 Exiting Stop Mode The MCU exits stop mode by a reset or peripheral function interrupt. Figure 10.15 shows the Time from Stop Mode to Interrupt Routine Execution. When using a peripheral function interrupt to exit ...
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R8C/2A Group, R8C/2B Group Figure 10.16 shows the State Transitions in Power Control Mode. State Transitions in Power Control Mode Standard operating mode CM14 = 0 OCD2 = 1 FRA01 = 0 High-speed clock mode CM05 = 0 CM07 = ...
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R8C/2A Group, R8C/2B Group 10.6 Oscillation Stop Detection Function The oscillation stop detection function detects the stop of the XIN clock oscillating circuit. The oscillation stop detection function can be enabled and disabled by the OCD0 bit in the OCD ...
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R8C/2A Group, R8C/2B Group Table 10.6 Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, and Voltage Monitor 2 Interrupts Generated Interrupt Source Oscillation stop detection ((a) or (b)) Watchdog timer Voltage monitor 1 Voltage monitor 2 ...
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R8C/2A Group, R8C/2B Group Interrupt sources judgement NO OCD3 = 1 ? (XIN clock stopped) YES (oscillation stop detection interrupt enabled) and OCD2 = 1 (on-chip oscillator clock selected as system clock) ? Set OCD1 bit to 0 (oscillation stop ...
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R8C/2A Group, R8C/2B Group 10.7 Notes on Clock Generation Circuit 10.7.1 Stop Mode When entering stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and the CM10 bit in the CM1 register to ...
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R8C/2A Group, R8C/2B Group 11. Protection The protection function protects important registers from being easily overwritten when a program runs out of control. Figure 11.1 shows the PRCR Register. The registers protected by the PRCR register are listed below. • ...
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R8C/2A Group, R8C/2B Group 12. Interrupts 12.1 Interrupt Overview 12.1.1 Types of Interrupts Figure 12.1 shows the types of Interrupts. Software (non-maskable interrupts) Interrupts Hardware NOTES: 1. Peripheral function interrupts in the MCU are used to generate peripheral interrupts. 2. ...
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R8C/2A Group, R8C/2B Group 12.1.2 Software Interrupts A software interrupt is generated when an instruction is executed. Software interrupts are non-maskable. 12.1.2.1 Undefined Instruction Interrupt The undefined instruction interrupt is generated when the UND instruction is executed. 12.1.2.2 Overflow Interrupt ...
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R8C/2A Group, R8C/2B Group 12.1.3 Special Interrupts Special interrupts are non-maskable. 12.1.3.1 Watchdog Timer Interrupt The watchdog timer interrupt is generated by the watchdog timer. For details, refer to 13. Watchdog Timer. 12.1.3.2 Oscillation Stop Detection Interrupt The oscillation stop ...
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R8C/2A Group, R8C/2B Group 12.1.5 Interrupts and Interrupt Vectors There are 4 bytes in each vector. Set the starting address of an interrupt routine in each interrupt vector. When an interrupt request is acknowledged, the CPU branches to the address ...
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R8C/2A Group, R8C/2B Group 12.1.5.2 Relocatable Vector Tables The relocatable vector tables occupy 256 bytes beginning from the starting address set in the INTB register. Table 12.2 lists the Relocatable Vector Tables. Table 12.2 Relocatable Vector Tables Interrupt Source Address ...
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R8C/2A Group, R8C/2B Group 12.1.6 Interrupt Control The following describes enabling and disabling the maskable interrupts and setting the priority for acknowledgement. The explanation does not apply to nonmaskable interrupts. Use the I flag in the FLG register, IPL, and ...
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R8C/2A Group, R8C/2B Group (1) Interrupt Control Register TRCIC TRD0IC TRD1IC SSUIC/IICIC Bit Symbol ILVL0 ILVL1 ILVL2 IR — (b7-b4) NOTES: 1. Rew rite the interrupt control register w hen the interrupt ...
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R8C/2A Group, R8C/2B Group INTi Interrupt Control Register (i Symbol INT2IC INT1IC INT3IC INT0IC Bit Symbol ILVL0 ILVL1 ILVL2 IR POL — (b5) — (b7-b6) NOTES: 1. Only 0 ...
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R8C/2A Group, R8C/2B Group 12.1.6.1 I Flag The I flag enables or disables maskable interrupts. Setting the I flag to 1 (enabled) enables maskable interrupts. Setting the I flag to 0 (disabled) disables all maskable interrupts. 12.1.6.2 IR Bit The ...
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R8C/2A Group, R8C/2B Group 12.1.6.4 Interrupt Sequence An interrupt sequence is performed between an interrupt request acknowledgement and interrupt routine execution. When an interrupt request is generated while an instruction is being executed, the CPU determines its interrupt priority level ...
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R8C/2A Group, R8C/2B Group 12.1.6.5 Interrupt Response Time Figure 12.7 shows the Interrupt Response Time. The interrupt response time is the period between an interrupt request generation and the execution of the first instruction in the interrupt routine. The interrupt ...
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R8C/2A Group, R8C/2B Group 12.1.6.7 Saving a Register In the interrupt sequence, the FLG register and PC are saved to the stack. After an extended 16 bits, 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order ...
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R8C/2A Group, R8C/2B Group 12.1.6.8 Returning from an Interrupt Routine When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC, which have been saved to the stack, are automatically restored. The program, ...
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R8C/2A Group, R8C/2B Group 12.1.6.10 Interrupt Priority Judgement Circuit The interrupt priority judgement circuit selects the highest priority interrupt, as shown in Figure 12.11. Priority level of interrupt A/D conversion Compare 0 Timer RB Timer RA Timer RF Timer RC ...
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R8C/2A Group, R8C/2B Group 12.2 INT Interrupt 12.2.1 INTi Interrupt ( The INTi interrupt is generated by an INTi input. When using the INTi interrupt, the INTiEN bit in the INTEN register is set to 1 ...
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R8C/2A Group, R8C/2B Group External Input Enable Register Symbol INTEN Bit Symbol INT0EN INT0PL INT1EN INT1PL INT2EN INT2PL INT3EN INT3PL NOTES: 1. When setting the INTiPL bit ( ...
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R8C/2A Group, R8C/2B Group _____ INT Input Filter Select Register Symbol INTF Bit Symbol INT0F0 INT0F1 INT1F0 INT1F1 INT2F0 INT2F1 INT3F0 INT3F1 Figure 12.14 INTF Register Timer RA I/O Control Register b7 ...
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R8C/2A Group, R8C/2B Group 12.2.2 INTi Input Filter ( The INTi input contains a digital filter. The sampling clock is selected by bits INTiF1 to INTiF0 in the INTF register. The INTi level is sampled every ...
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R8C/2A Group, R8C/2B Group 12.3 Key Input Interrupt A key input interrupt request is generated by one of the input edges of pins K10 to K13. The key input interrupt can be used as a key-on wake-up function to exit ...
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R8C/2A Group, R8C/2B Group (1) Key Input Enable Register Symbol KIEN Bit Symbol KI0EN KI0PL KI1EN KI1PL KI2EN KI2PL KI3EN KI3PL NOTE: 1. The IR bit in the KUPIC register may be ...
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R8C/2A Group, R8C/2B Group 12.4 Address Match Interrupt An address match interrupt request is generated immediately before execution of the instruction at the address indicated by the RMADi register ( 1). This interrupt is used as a ...
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R8C/2A Group, R8C/2B Group Address Match Interrupt Enable Register Symbol AIER Bit Symbol AIER0 AIER1 — (b7-b2) Address Match Interrupt Register i (b23) (b19) (b16) (b15 ...
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R8C/2A Group, R8C/2B Group 12.5 Timer RC Interrupt, Timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupts, and I Multiple Interrupt Request Sources) The timer RC interrupt, timer RD (channel 0) interrupt, timer RD (channel 1) interrupt, clock ...
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R8C/2A Group, R8C/2B Group As with other maskable interrupts, the timer RC interrupt, timer RD (channel 0) interrupt, timer RD (channel 1) interrupt, clock synchronous serial I/O with chip select interrupt, and I the combination of the I flag, IR ...
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R8C/2A Group, R8C/2B Group 12.6 Notes on Interrupts 12.6.1 Reading Address 00000h Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads interrupt information (interrupt number and interrupt request level) from 00000h ...
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R8C/2A Group, R8C/2B Group 12.6.4 Changing Interrupt Sources The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source changes. When using an interrupt, set the IR bit to 0 (no interrupt ...
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R8C/2A Group, R8C/2B Group 12.6.5 Changing Interrupt Control Register Contents (a) The contents of an interrupt control register can only be changed while no interrupt requests corresponding to that register are generated. If interrupt requests may be generated, disable interrupts ...
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R8C/2A Group, R8C/2B Group 13. Watchdog Timer The watchdog timer is a function that detects when a program is out of control. Use of the watchdog timer is recommended to improve the reliability of the system. The watchdog timer contains ...
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R8C/2A Group, R8C/2B Group Prescaler CPU clock Write to WDTR register Internal reset signal (“L” active) NOTE: 1. When the CSPRO bit is set to 1 (count source protection mode enabled), 0FFFh is set. Figure 13.1 Block Diagram of Watchdog ...
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R8C/2A Group, R8C/2B Group Watchdog Timer Reset Register b7 b0 Symbol WDTR When 00h is w ritten before w riting FFh, the w atchdog timer is reset. The default value of the w atchdog timer is 7FFFh w hen count ...
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R8C/2A Group, R8C/2B Group Count Source Protection Mode Register Symbol CSPR Bit Symbol — (b6-b0) CSPRO NOTES: 1. When ritten to the ...
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R8C/2A Group, R8C/2B Group 13.1 Count Source Protection Mode Disabled The count source of the watchdog timer is the CPU clock when count source protection mode is disabled. Table 13.2 lists the Watchdog Timer Specifications (with Count Source Protection Mode ...
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R8C/2A Group, R8C/2B Group 13.2 Count Source Protection Mode Enabled The count source of the watchdog timer is the low-speed on-chip oscillator clock when count source protection mode is enabled. If the CPU clock stops when a program is out ...
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R8C/2A Group, R8C/2B Group 14. Timers The MCU has two 8-bit timers with 8-bit prescalers, three 16-bit timers, and a timer with a 4-bit counter and an 8-bit counter. The two 8-bit timers with 8-bit prescalers are timer RA and ...
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R8C/2A Group, R8C/2B Group Table 14.1 Functional Comparison of Timers (1) Item Timer RA Configuration 8-bit timer with 8-bit prescaler (with reload register) Count Decrement Count sources • f1 • f2 • f8 • fOCO • fC32 Function Count of ...
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R8C/2A Group, R8C/2B Group Table 14.2 Functional Comparison of Timers (2) Item Timer RA Input pin TRAIO Output pin TRAO TRAIO Related interrupt Timer RA interrupt, INT1 interrupt Timer stop Provided NOTE: 1. The underflow interrupt can be set to ...
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R8C/2A Group, R8C/2B Group 14.1 Timer RA Timer 8-bit timer with an 8-bit prescaler. The prescaler and timer each consist of a reload register and counter. The reload register and counter are allocated at the same address, ...
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R8C/2A Group, R8C/2B Group (4) Timer RA Control Register Symbol TRACR Bit Symbol TSTART TCSTF TSTOP — (b3) TEDGF TUNDF — (b7-b6) NOTES: 1. Refer to 14.1.6 Notes on Tim er RA. ...
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R8C/2A Group, R8C/2B Group (1) Timer RA Mode Register Symbol TRAMR Bit Symbol TMOD0 TMOD1 TMOD2 — (b3) TCK0 TCK1 TCK2 TCKCUT NOTE: 1. When both the TSTART and TCSTF bits in ...
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R8C/2A Group, R8C/2B Group 14.1.1 Timer Mode In this mode, the timer counts an internally generated count source (refer to Table 14.3 Timer Mode Specifications). Figure 14.4 shows TRAIOC Register in Timer Mode. Table 14.3 Timer Mode Specifications Item Count ...
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R8C/2A Group, R8C/2B Group 14.1.1.1 Timer Write Control during Count Operation Timer RA has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each consist of a reload register and a counter. When writing to ...
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R8C/2A Group, R8C/2B Group 14.1.2 Pulse Output Mode In pulse output mode, the internally generated count source is counted, and a pulse with inverted polarity is output from the TRAIO pin each time the timer underflows (refer to Table 14.4 ...
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R8C/2A Group, R8C/2B Group Timer RA I/O Control Register Symbol TRAIOC Bit Symbol TEDGSEL TOPCR TOENA TIOSEL TIPF0 TIPF1 — (b7-b6) Figure 14.6 TRAIOC Register in Pulse Output Mode Rev.2.00 ...
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R8C/2A Group, R8C/2B Group 14.1.3 Event Counter Mode In event counter mode, external signal inputs to the INT1/TRAIO pin are counted (refer to Table 14.5 Event Counter Mode Specifications). Figure 14.7 shows TRAIOC Register in Event Counter Mode. Table 14.5 ...
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R8C/2A Group, R8C/2B Group Timer RA I/O Control Register Symbol TRAIOC Bit Symbol TEDGSEL TOPCR TOENA TIOSEL TIPF0 TIPF1 — (b7-b6) NOTE: 1. When the same value from the TRAIO pin ...
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R8C/2A Group, R8C/2B Group 14.1.4 Pulse Width Measurement Mode In pulse width measurement mode, the pulse width of an external signal input to the INT1/TRAIO pin is measured (refer to Table 14.6 Pulse Width Measurement Mode Specifications). Figure 14.8 shows ...
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R8C/2A Group, R8C/2B Group Timer RA I/O Control Register Symbol TRAIOC Bit Symbol TEDGSEL TOPCR TOENA TIOSEL TIPF0 TIPF1 — (b7-b6) NOTE: 1. When the same value from the TRAIO ...
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R8C/2A Group, R8C/2B Group n = high level: the contents of TRA register, low level: the contents of TRAPRE register FFFFh n 0000h Set program 1 TSTART bit in TRACR register 0 1 Measured pulse (TRAIO pin ...
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R8C/2A Group, R8C/2B Group 14.1.5 Pulse Period Measurement Mode In pulse period measurement mode, the pulse period of an external signal input to the INT1/TRAIO pin is measured (refer to Table 14.7 Pulse Period Measurement Mode Specifications). Figure 14.10 the ...
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R8C/2A Group, R8C/2B Group Timer RA I/O Control Register Symbol TRAIOC Bit Symbol TEDGSEL TOPCR TOENA TIOSEL TIPF0 TIPF1 — (b7-b6) NOTE: 1. When the same value from the TRAIO ...
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R8C/2A Group, R8C/2B Group Underflow signal of timer RA prescaler 1 TSTART bit in TRACR register 0 Starts counting 1 Measurement pulse (TRAIO pin input) 0 Contents of TRA Contents of read-out buffer (1) 1 TEDGF bit in TRACR register ...
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R8C/2A Group, R8C/2B Group 14.1.6 Notes on Timer RA • Timer RA stops counting after a reset. Set the values in the timer RA and timer RA prescalers before the count starts. • Even if the prescaler and timer RA ...
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R8C/2A Group, R8C/2B Group 14.2 Timer RB Timer 8-bit timer with an 8-bit prescaler. The prescaler and timer each consist of a reload register and counter (refer to Tables 14.8 to 14.11 the Specifications of Each Mode). ...
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R8C/2A Group, R8C/2B Group Timer RB Control Register Symbol TRBCR Bit Symbol TSTART TCSTF TSTOP — (b7-b3) NOTES: 1. Refer to 14.2.5 Notes on Tim er RB. 2. When the TSTOP bit ...
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R8C/2A Group, R8C/2B Group Timer RB I/O Control Register Symbol TRBIOC Bit Symbol TOPL TOCNT INOSTG INOSEG — (b7-b4) Timer RB Mode Register Symbol ...
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R8C/2A Group, R8C/2B Group Timer RB Prescaler Register b7 b0 Timer mode Programmable w aveform generation mode Programmable one-shot generation mode Programmable w ait one-shot generation mode NOTE: 1. When the TSTOP bit in the TRBCR register is set to ...
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R8C/2A Group, R8C/2B Group 14.2.1 Timer Mode In timer mode, a count source which is internally generated or timer RA underflows are counted (refer to Table 14.8 Timer Mode Specifications). Registers TRBOCR and TRBSC are not used in timer mode. ...