R5F212B7SNFP#U0 Renesas Electronics America, R5F212B7SNFP#U0 Datasheet - Page 344

• Manufacturer Part Number: R5F212B7SNFP#U0
• Description: IC R8C/2B MCU FLASH 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Br

Specifications of R5F212B7SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 55
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2A Group, R8C/2B Group
Rev.2.00
REJ09B0324-0200
Table 14.48
i = 0 or 1, j = either A, B, C, or D
Count sources
Count operations
PWM waveform
Count start condition
Count stop conditions
Interrupt request generation
timing
TRDIOA0, TRDIOB0 pin
functions
TRDIOC0, TRDIOD0, TRDIOA1
to TRDIOD1 pin functions
INT0 pin function
Read from timer
Write to timer
Select functions
Nov 26, 2007
PWM3 Mode Specifications
Item
Page 322 of 580
f1, f2, f4, f8, f32, fOCO40M
The TRD0 register is incremented (the TRD1 is not used).
PWM period: 1/fk × (m+1)
Active level width of TRDIOA0 output: 1/fk × (m-n)
Active level width of TRDIOB0 output: 1/fk × (p-q)
1 (count starts) is written to the TSTART0 bit in the TRDSTR register.
• 0 (count stops) is written to the TSTART0 bit in the TRDSTR register
• When the CSEL0 bit in the TRDSTR register is set to 0, the count
• Compare match (The content of the TRDi register matches content
• The TRD0 register overflows
PWM output
Programmable I/O port
Programmable I/O port, pulse output forced cutoff signal input, or
INT0 interrupt input
The count value can be read by reading the TRD0 register.
The value can be written to the TRD0 register.
• Pulse output forced cutoff signal input (Refer to 14.4.4 Pulse
• Buffer Operation (Refer to 14.4.2 Buffer Operation.)
• Active level selectable by pin
fk: Frequency of count source
m: Value set in the TRDGRA0 register
n: Value set in the TRDGRA1 register
p: Value set in the TRDGRB0 register
q: Value set in the TRDGRB1 register
when the CSEL0 bit in the TRDSTR register is set to 1.
The PWM output pin holds output level before the count stops
stops at compare match with the TRDGRA0 register.
The PWM output pin holds level after output change by compare
match.
of the TRDGRji register.)
Output Forced Cutoff.)
TRDIOA0 output
TRDIOB0 output
m+1
n+1
p+1
q+1
p-q
Specification
(When “H” is selected as the active level)
m-n
14. Timers